Shielded bitline architecture for dynamic random access memory (dram) arrays

Abstract

A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

Description

technical field [0001] The present invention relates to the field of integrated circuit (IC) memory devices, including dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded dynamic random access memory. In particular, it relates to a shielded bit line structure for a dynamic random access memory array. Background technique [0002] There are a variety of DRAM base devices or integrated circuits with embedded memory arrays, including Extended Data Output (EDO) DRAM, Synchronous DRAM (SDRAM), Double Data Rate (DDR) DRAM Random Access Memory, DDR3 Dynamic Random Access Memory (DDR3 DRAM), and the like. Regardless of configuration, the main purpose of DRAM is to store data. The main function of the memory is that data can be written into the memory, read from it or updated periodically to maintain the integrity of the stored data. In today's high-density designs, each DRAM cell typically consists of a single access transistor ...

AI Technical Summary

Problems solved by technology

However, the layout of bitline twists consumes on-chip die area, typically about six bitline pitches, thereby resulting in an increase in the total DRAM array area required, with a concomitant increase in device cost

In addition, when the twisting of the bit lines ensures that the bit line to bit line coupling becomes a "common mode", the coupling still cannot be reduced

Images