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Simulation circuit of PCI EXPRESS endpoint and downstream port for a PCI EXPRESS switch

A technology of analog circuits and port circuits, which is applied in the communication field of processing type applications, and can solve problems such as the failure of endpoints

Inactive Publication Date: 2007-03-21
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, only PC-to-PCI bridges representing downstream ports of this switch may appear on the internal bus, endpoints represented by configuration space headers of type O cannot appear on the internal bus
[0005] The existence of these and other limitations presents a challenge to implementing integrated devices with PCI Express communication

Method used

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  • Simulation circuit of PCI EXPRESS endpoint and downstream port for a PCI EXPRESS switch
  • Simulation circuit of PCI EXPRESS endpoint and downstream port for a PCI EXPRESS switch
  • Simulation circuit of PCI EXPRESS endpoint and downstream port for a PCI EXPRESS switch

Examples

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Embodiment Construction

[0020] Although the present invention is susceptible to various modifications and alternatives, the details thereof have been shown by way of examples in the accompanying drawings and will be described in detail. It should be understood, however, that the invention is not limited to the particular Examples described. On the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the scope of the invention as defined by the appended claims.

[0021] The present invention is believed to be applicable to various circuits and methods involving electronic communications, and particularly to those circuits and methods involving communications between endpoint type devices and a communication bus (eg, within a PCI Express hub). While the present invention is not limited to this application, an understanding of various aspects of the invention can be better gained through a discussion of examples within this context.

[0022] According to on...

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Abstract

Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement (100) is adapted to emulate two virtually separate hierarchical subsystems (121, 146) in a single hardware block (120). This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices.

Description

technical field [0001] The present invention relates generally to communication for processing type applications, and more particularly to communication methods and devices using PCIExpress type links. Background technique [0002] PCI (Peripheral Component Interconnect) is an interconnection system between a microprocessor and attached devices in which expansion slots are closely spaced for high speed operation. By using PCI, computers can support new PCI cards while continuing to support older standard Industry Standard Architecture (ISA) expansion cards. PCI is designed to be independent of the microprocessor design and synchronized with the clock speed of the microprocessor. PCI uses the current path (on the multipoint bus) to send address and data signals, sending the address on one clock cycle and sending the data on the next clock cycle. The PCI bus can accommodate adapters that require fast inter-access and / or fast access to system memory, and the host processor ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40
CPCG06F13/4022G06F13/40G06F13/14G06F13/42
Inventor D·R·伊沃伊J·M·罗斯
Owner NXP BV
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