Chip structure and stacked chip packing structure

Abstract

The invention is concerned with the CMOS chip structure, including: the main body of the CMOS chip, the first protecting layer, the re-configuring circuit layer, and the second protecting layer; it is: the main body of the CMOS chip is with the welding jointing area, near the single side edge or neighbor both sides of the main body of the CMOS chip, the main body of the CMOS chip is with the first welding underlay in several welding jointing area and the second welding underlay located out of several welding jointing area; the first protecting layer with several first hatches configures on the main body of the CMOS chip in order to emerge the first welding underlay and the second welding underlay; the re-configuring circuit layer with several third welding underlay located in the welding line jointing area configures on the first protecting layer, extends form the second welding underlay to the welding line jointing area; the second protecting layer with several second hatches covers on the re-configuring circuit layer in order to emerge the fires welding underlay and the third welding underlay.

Description

technical field [0001] The present invention relates to a chip structure and its chip package structure, and in particular to a chip structure with reconfiguration circuit layers and a stacked chip package structure formed by stacking them. Background technique [0002] In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. In terms of product appearance, the design of electronic products is also moving towards the trend of light, thin, short and small. In order to achieve the above goals, many companies incorporate the concept of systemization when designing circuits, so that a single chip (a chip is a chip, hereinafter referred to as a chip) can have multiple functions to save configuration in electronic products. number of chips. In addition, as far as electronic packaging technology is concerned, in order to meet the design trend of light, thin, short, and small, the packaging design concept of multi-chip ...

AI Technical Summary

Problems solved by technology

However, when the conventional technology stacks a plurality of chips of different sizes into the stacked chip package structure 100' in the above-mentioned manner, since the size of the chips on the upper layer must be smaller, the stacked chip package structure 100' has chips. stack limit

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