Lock detecting circuit and method for phase lock loop system
A phase-locked loop, lock-in detection technology, applied in electronic circuit testing, electrical components, automatic control of power, etc., can solve problems such as inability to adjust, the tolerance of phase error cannot be changed flexibly, process variation or temperature changes, etc.
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[0041] The so-called logically asserted state in this specification (including claims) refers to a state representing a logic "1", which may be a high level state in a positive logic system or a negative logic system. ) in the low state. A logic signal is asserted to indicate that the logic signal is set to a logic "1" state.
[0042] FIG. 3 shows a schematic diagram of a lock detection circuit 300 according to an embodiment of the invention. Basically, the lock detection circuit 300 is connected to the typical PLL system 100 shown in FIG. 1 (but not limited thereto) to detect whether the PLL system 100 is in a locked state. Specifically, the lock detection circuit 300 receives the reference clock signal RCLK, the voltage-controlled oscillation frequency-divided clock signal VCLK, and the voltage-controlled oscillation clock signal VCO_CLOCK in the typical PLL system 100 of FIG. 1 . As long as the frequency is higher than the input clock signal P of the phase-locked loop sys...
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