Unlock instant, AI-driven research and patent intelligence for your innovation.

Lock detecting circuit and method for phase lock loop system

A phase-locked loop, lock-in detection technology, applied in electronic circuit testing, electrical components, automatic control of power, etc., can solve problems such as inability to adjust, the tolerance of phase error cannot be changed flexibly, process variation or temperature changes, etc.

Active Publication Date: 2007-04-11
VIA TECH INC
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The traditional lock detection circuit 200 shown in FIG. 2A is often caused by component matching problems, process variations or temperature changes, even though the relative PLL system 100 is locked, but the lock detection circuit 200 still detects that it cannot negligible static phase difference
In other words, the phase error tolerance of the conventional lock detection circuit 200 often does not meet the actual requirements
Moreover, the phase error tolerance of the traditional lock detection circuit 200 shown in FIG. 2A cannot be flexibly changed. This shortcoming makes it impossible for the traditional lock detection circuit 200 to adjust the applicable phase error tolerance according to actual needs to meet the needs of different applications.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Lock detecting circuit and method for phase lock loop system
  • Lock detecting circuit and method for phase lock loop system
  • Lock detecting circuit and method for phase lock loop system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0041] The so-called logically asserted state in this specification (including claims) refers to a state representing a logic "1", which may be a high level state in a positive logic system or a negative logic system. ) in the low state. A logic signal is asserted to indicate that the logic signal is set to a logic "1" state.

[0042] FIG. 3 shows a schematic diagram of a lock detection circuit 300 according to an embodiment of the invention. Basically, the lock detection circuit 300 is connected to the typical PLL system 100 shown in FIG. 1 (but not limited thereto) to detect whether the PLL system 100 is in a locked state. Specifically, the lock detection circuit 300 receives the reference clock signal RCLK, the voltage-controlled oscillation frequency-divided clock signal VCLK, and the voltage-controlled oscillation clock signal VCO_CLOCK in the typical PLL system 100 of FIG. 1 . As long as the frequency is higher than the input clock signal P of the phase-locked loop sys...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention relates to a locking detection circuit and a method for phase-locking loop system including a delay unit and an established logic unit, in which, the delay unit inputs phase error signals of the system to generate a current phase error signal and generate at least one delay phase error signal based on it, the established logic unit generates and sets up an un-locked instruction signal based on the current phase error signal and the delayed phase error signal, if said un-locked instruction signal is not established in a specific number of the pulse time, then a loop lock instruction signal is generated, which can adjust the tolerance to the error of static phase difference flexibly.

Description

technical field [0001] The present invention relates to a circuit state detection circuit and method, in particular to a lock detecting circuit and method for a phase lock loop (PLL) system. Background technique [0002] 1 shows a system block diagram of a typical PLL system 100 in the prior art, which includes a pre-divider (pre-divider) 110, a phase frequency detector (phase frequency detector or PFD) 120, a charge pump (charge pump) 130 , a low pass filter (low pass filter) 140 , a voltage controlled oscillator (voltage controlled oscillator or VCO) 150 , a post-divider (post-divider) 160 and a feedback divider (feedback divider) 170 . The prescaler 110 receives the input clock signal P IN , and output a frequency-divided reference clock signal RCLK to the phase frequency detector 120 . The phase frequency detector 120 is connected to the feedback divider 170 to receive the frequency-divided clock signal VCLK of the voltage-controlled oscillation. The phase frequency d...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08H03L7/00H03L7/18G01R31/28
Inventor 黄钧哲
Owner VIA TECH INC