Wafer-level opto-electronic testing apparatus and method

Abstract

A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The optoelectronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of US Provisional Application No. 60 / 551,316, filed March 8, 2004. technical field

[0003] The present invention relates to apparatus for wafer-level testing, and more particularly, to the ability to provide optical, electrical, and optoelectronic testing of components formed on silicon-on-insulator (SOI) structures using a single test element. Background technique

[0004] In the semiconductor industry, relatively large silicon wafers (typically on the order of several inches in diameter) are processed to form many identical integrated circuits. Once the wafer has been fully processed, it is diced into pieces to form individual integrated circuits. In most cases, hundreds of identical lines are formed across the surface of the wafer. If the performance of the individual lines is not tested prior to dicing, the "bad" die may be further processed and packaged, wasting valuable time...

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