Fraction frequency-division circuit applied for phase-locked ring circuit

Abstract

Being applicable to the phase lock ring (PLR) circuit, the fraction frequency dividing circuit uses Hf signal of processing voltage-controlled oscillator (VCO) to raise reference frequency of PLR effectively, and reduce influence noise from signal source without lowering resolution. The fraction frequency dividing circuit includes a pre frequency dividing circuit (PFDC) and a counter. When control end is in high level, PFDC divides frequency of output of VCO in PLR circuit by using modulus P+1, and when control end is in low level, PFDC divides frequency of output of VCO in PLR circuit by using modulus P. the counter works according to following logic: after resetting system, sending a signal in high to control end of PFDC to start counting; when reaching to a prearranged value, sending a signal in low to control end of PFDC; when reaching to another prearranged value, resetting system and counter. In rising edge and falling edge of each clocking, the counter counts.

Description

technical field [0001] The invention relates to a phase-locked loop design in the field of integrated circuit design, in particular to a fractional frequency division circuit applied to a phase-locked loop circuit. Background technique [0002] Phase-locking technology is widely used in the communication field, and the performance requirements are getting higher and higher. As the main part of the frequency synthesizer, the phase noise of the phase-locked loop becomes a very important index, because it determines whether the communication frequency band can be effectively used in a strong interference environment. [0003] In order to get lower phase noise, a broadband PLL can effectively suppress the noise generated from the voltage-controlled oscillator (VCO), but the influence of the reference clock noise generated from the crystal oscillator becomes more important. Compared with narrow-band PLLs, the noise of the reference clock is less likely to be suppressed. [0004...

AI Technical Summary

Problems solved by technology

[0004] At the same time, in the field of communication, in order to avoid the use of a very high counting frequency divider, a fixed frequency divider is often connected behind the voltage controlled oscillator, but this reduces the resolution of the output frequency

As shown in Figure 1, the prescaler circuit can ensure the normal operation of the high-frequency phase-locked loop, but because the frequency division number is fixed, the resolution of the output frequency (fo) is reduced

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