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Deposition of nano-crystal silicon using a single wafer chamber

A technology of nanocrystalline silicon and single wafer, applied in nanotechnology, nanotechnology, nanotechnology for materials and surface science, etc., can solve the problems of high wafer deposition rate and difficulty in obtaining uniform thickness

Inactive Publication Date: 2007-06-27
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the deposition rate of the wafer placed close to the entrance is high, and it is difficult to obtain a uniform thickness

Method used

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  • Deposition of nano-crystal silicon using a single wafer chamber
  • Deposition of nano-crystal silicon using a single wafer chamber
  • Deposition of nano-crystal silicon using a single wafer chamber

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Embodiment Construction

[0014] In the following specification, in order to provide a comprehensive understanding of the embodiments of the present invention, numerous specific descriptions will be made such as examples of specific materials or components. It will be apparent, however, to those of ordinary skill in the art that the specific description may not be employed to practice the embodiments of the invention. In other embodiments, well-known elements or methods have not been described in detail in order to avoid unnecessarily obscuring the embodiments of the present invention.

[0015] The terms "on", "upper", "under", "between" and "adjacent" as used herein refer to a layer or element with reference to The relative position of another layer or element. Thus, a first element disposed on, above or below another element may be in direct contact with the first element or may have one or more intervening elements. In addition, an element positioned near or adjacent to another element may be dire...

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PUM

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Abstract

Numerous embodiments of a method for depositing a layer of nano-crystal silicon on a substrate. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300 DEG C. to about 490 DEG C. A silicon source is also fed into the single wafer chamber.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor technology, and more particularly, to a method and device for controlling the crystal structure of a silicon thin film. Background technique [0002] Polysilicon thin films formed by chemical vapor deposition (CVD) are widely used in the manufacture of integrated circuits such as microprocessors and memories. Polysilicon thin film deposition processes require suitable physical, chemical and product value properties. For example, product value attributes include polysilicon thin films of uniform thickness and composition (eg, within wafers and between wafers), low particulate chemical contamination, and high manufacturing throughput. When these characteristics are satisfied, device wafers with high electrical performance, high reliability and high yield can be manufactured at low cost. [0003] In a CVD process, reactive gases and diluted inert gases of given composition and flo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C23C16/24
CPCC23C16/24Y10S977/814B82Y30/00B82Y40/00
Inventor 希比·J·帕纳伊尔李明树林·王乔纳森·C·皮克林
Owner APPLIED MATERIALS INC