Semiconductor device with superior crack resistivity in the metallization system

Abstract

A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and / or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and / or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.

Description

BACKGROUND[0001]1. Field of the Disclosure[0002]Generally, the present disclosure relates to the technology of semiconductor devices including metallization systems and a pad structure for connecting to a package.[0003]2. Description of the Related Art[0004]Semiconductor devices typically include, depending on the degree of complexity, a more or less number of semiconductor-based circuit elements, such as field effect transistors, bipolar transistors and the like, typically in combination with resistors, capacitors and the like. In most approaches, these circuit elements may be formed in and on a corresponding semiconductor layer, such as a silicon layer, a silicon / germanium layer or any other appropriate semiconductor material layer, wherein, layer after layer, respective device patterns may be formed and / or processed in accordance with a specified design and related design rules by using well-established, yet sophisticated, manufacturing techniques, such as photolithography, etchi...

AI Technical Summary

Benefits of technology

This configuration significantly enhances the mechanical robustness of the semiconductor device, reducing the probability of crack propagation and improving the reliability and performance of the metallization system by increasing the energy required for crack generation and propagation.

Problems solved by technology

Consequently, in many cases, the resulting metallization system represents a complex stack of metallization layers, at least some of which may be formed on the basis of critical materials suffering from less pronounced mechanical stability compared to conventional dielectric materials, such as silicon dioxide, silicon nitride and the like.

Consequently, when encountering certain loads during the further processing or during operation of such semiconductor devices, including respective metallization systems, yield loss and / or premature failure of semiconductor devices may be observed, which may be frequently caused by cracks forming in sensitive dielectric materials, which may not only result in a reduction of mechanical stability, but may also impart less electrical strength to respective portions of the metallization system.

Also, in this case, significant mechanical stress may be induced in the passivation level of the semiconductor device, which may comprise polyimide and the like, having superior passivation characteristics, yet exhibiting a relatively brittle behavior when exposed to mechanical stress.

As discussed above, any such crack-related defects in the metallization system may result in yield loss, premature failure or reduced reliability of the semiconductor device under consideration.

In many approaches, the respective contact pads may have to be placed with tight spacing in the passivation level so as to comply with design criteria such that, for instance, providing respective bond pads as substantially “isolated” structures for enhancing mechanical robustness may not represent a viable option.

In other cases, in addition to contact pads, relatively thick metal lines, for instance for RF applications, may have to be frequently implemented, thereby exacerbating the problem of crack formation in the passivation layer and underlying metallization layers even further.

U.S. Patent Publication No. 2015 / 0061156 discloses a manufacturing technique for forming a bond pad, for instance, for wire bonding, by reducing the number of dielectric layers in the passivation level of the semiconductor device, however, without specifically addressing the problem of crack formation in the passivation material and the metallization layers positioned below the passivation layer.

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