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Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer

a technology of metal interconnect layer and semiconductor device, which is applied in the details of semiconductor/solid-state devices, semiconductor devices, electrical devices, etc., can solve the problem of impossible normal operation of semiconductor chips

Inactive Publication Date: 2002-05-02
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This problem is serious when the upper width of a trench is larger than the lower width, as shown in FIG. 2.
When such lifting of a metal connection occurs in a trench, the contact between a via and the metal interconnect is unsatisfactory, so that normal operation of semiconductor chips is impossible.

Method used

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  • Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer
  • Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer
  • Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer

Examples

Experimental program
Comparison scheme
Effect test

embodiment 1

[0046] Method Embodiment 1

[0047] An embodiment of the metal interconnect formation according to the present invention is illustrated in FIGS. 8A through 8D. Referring to FIG. 8A, an ILD film 102 is formed over a semiconductor wafer 100. It is preferable that the ILD film 102 be formed of a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer. The semiconductor wafer 100 may be a substrate as a stack of an insulation layer, such as a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer, and a silicon nitride layer deposited in sequence over a predetermined underlying layer.

[0048] Referring to FIG. 8B, a photoresist pattern 104 is formed on the ILD film 102 by a photolighography process. A portion of the ILD film 102 is etched using the photoresist pattern 104 as an etching mask to form a shallow trench 106. A polymer layer 105 acting as an etch barrier is spontaneously formed on the sidewalls of the shallow trench 106. It is preferable that the height of the shallow trenc...

embodiment 2

[0053] Method Embodiment 2

[0054] Another embodiment of the metal interconnect formation according to the present invention is illustrated by steps in FIGS. 9A through 9D. Referring to FIG. 9A, a first ILD film 201 and a second ILD film 202 are deposited over a semiconductor wafer 200 in sequence. It is preferable that the first ILD film 201 is formed of a material such as a FOX layer or HOSP layer, having a higher etch ratio and smaller resistance constant than those of the material for the second ILD film 202. The second ILD film 202 may be formed of a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer. The thickness of the second ILD film 202 may be in the range of about 20-70% of the sum of the thicknesses of the first and second ILD films 201 and 202. The material used for the first ILD film 201, such as FOX layer or HOSP layer, has a smaller dielectric constant than the USG layer or SOG layer used as the second ILD film 201, thereby lowering parasitic capacitance of the...

embodiment 3

[0058] Method Embodiment 3

[0059] Another embodiment of the metal interconnect formation according to the present invention is illustrated by steps in FIGS. 10A through 10D. Referring to FIG. 10A, an ILD film 302 is formed over a semiconductor wafer 300. It is preferable that the ILD film 302 be formed of a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer. The semiconductor wafer 300 may be a substrate as a stack of an insulation layer, such as a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer, and a silicon nitride layer deposited in sequence over a predetermined underlying layer.

[0060] Referring to FIG. 10B, a photoresist pattern 304 that defines a metal interconnect region is formed on the ILD film 302 by a photolighography process. The upper portion of the ILD film 302 is etched using the photoresist pattern 304 as an etch mask to form a first trench 306. During the etching to the upper portion of the ILD film 302, a polymer layer 305' acting as an etch barri...

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PUM

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Abstract

A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the invention, the middle portion of the metal interconnect layer is wider than the upper and lower portions of the metal interconnect layer.

Description

[0001] 1. Field of the Invention[0002] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a metal interconnect layer of a semiconductor device and a method for forming the metal interconnect layer.[0003] 2. Description of the Related Art[0004] For higher integration density and rapid operation of integrated circuit chips, semiconductor integration techniques have been advanced. The size of chips has been decreased with a smaller design rule to satisfy the need for high integration level. To increase the operation speed of chips, performance of transistors has been enhanced by reducing the parasitic resistance and parasitic capacitance of the transistors.[0005] With regard to interconnection techniques for semiconductor devices, it is significant to design a high-performance transistor with a minimum resistance and parasitic capacitance, such that an RC level (resistance x capacitance) of a semiconductor device h...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/316H01L21/3205H01L21/768H01L23/52H01L23/528H01L23/532
CPCH01L23/53238H01L23/53266H01L21/31116H01L21/31138H01L23/5283H01L21/76804H01L21/76843H01L21/76844H01L21/31144H01L2924/0002H01L2924/00H01L21/28
Inventor AHN, JONG-HYON
Owner SAMSUNG ELECTRONICS CO LTD