Diffusion resistor/capacitor (DRC) non-aligned mosfet structure

Abstract

A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source / drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source / drain. The deeper emitter / collector increases the second trigger current of the NFET when used as an ESD protection device.

Description

[0001] 1. Field of the Invention[0002] This invention relates to semiconductor circuits and structures. More specifically, this invention relates to a non-aligned MOSFET structure and process using resistors as the diffusions and capacitors as the gate for electrostatic discharge (ESD) protection.[0003] 2. Description of Related Art[0004] Protection against ESD is a familiar problem in the design of semiconductor devices. It is common to use an NMOS FET device in bipolar mode (parasitic npn) with N+ type diffusions for the source and drain, and a channel formed in a P-well in a P-type substrate, as protection against ESD. In an NMOS FET, the source of the FET forms the emitter of the bipolar, the FET channel region between drain to source forms the base, and the drain forms the collector. When electron and holes are created by avalanche multiplication at the drain, the holes forward-bias the base-emitter junction and the parasitic bipolar turns on once the local substrate bios meets...

AI Technical Summary

Benefits of technology

[0015] Another object of the present invention is to provide a method and structure to increase the doping level in the emitter / collector and eliminate the extension region.

[0016] Finally, yet another object of the present is to provide a method and structure to eliminate the need for additional masks in forming an NFET ESD protection device.

Problems solved by technology

Protection against ESD is a familiar problem in the design of semiconductor devices.

In today's advanced CMOS technologies, the NFET device used in parasitic bipolar npn mode during an ESD event is of limited use due to its relatively low second trigger current (It2), also known as thermal runaway current.

Since the effective emitter area of the bipolar during avalanche conditions is formed in a shallow region, the current density becomes very large during an avalanche / ESD event and causes a significant temperature increase in the region.

The problem with the typical NFET device used for ESD protection thus becomes twofold.

This results in a high current density through this region during an ESD event.

Second, the lighter doping in the extension region, combined with the high current density during an ESD event, causes a significant increase in the temperature of the silicon where the bipolar action is occurring, compared to the temperature in that region if the extension is not present.

The drawback to this prior art is that the process requires an additional mask.

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