Multi-chip stack package and fabricating method thereof

Abstract

Abstract of Disclosure A multi-chip stack package having a substrate, a first chip, a second chip, a plurality of bumps, a plurality of junction interface bumps, a plurality of conductive wires, a first filler material, a second filler material and an encapsulating material is provided. The substrate has a substrate surface with a plurality of first contacts and a plurality of second contacts. The first chip has a first active surface with a plurality of bonding pads thereon and a first chip back surface. The first chip is positioned over the substrate surface. The second chip has a second active surface with a plurality of bonding pads thereon and a second chip back surface. The second chip is positioned over the first chip back surface. The bumps are positioned between the first bonding pads and the first contacts. The junction interface bumps are positioned between the first chip back surface and the second chip back surface. The conductive wires electrically connect the second bonding pads and the second contacts. The first filler material encloses the bumps and the second filler material encloses the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.

Description

Cross Reference to Related Applications[0001] This application claims the priority benefit of Taiwan application serial no. 91100096, filed January 7, 2002.Background of Invention[0002] Field of Invention[0003] The present invention relates to a multi-chip stack package. More particularly, the present invention relates to a multi-chip stack package and fabricating method thereof that can improve the quality of a multi-chip stack package.[0004] Description of Related Art[0005] As electronic technologies continue to advance, more personalized, multi-functional high-tech electronic products are being introduced into the market. The newer electronic products are characteristically smaller, lighter and slimmer so that the product will occupy less space and be more portable. In semiconductor manufacturing, many types of packages now incorporate a multi-chip concept so that volume occupation of an integrated circuit is reduced and electrical performance is improved. In a multi-chip stack p...

AI Technical Summary

Benefits of technology

0008] Accordingly, one object of the present invention is to provide a multi-chip stack package and a fabricating method thereof that can improve bonding quality of the multi-chip stack.

Problems solved by technology

However, if too much attaching pressure is applied to the second chip 140, some adhesive material 150 will bleed out.

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