Low jitter external clocking

Abstract

A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Description

FIELD OF THE INVENTION [0001] The invention relates generally to integrated circuits, and more particularly to low jitter external clocking. BACKGROUND [0002] Digital integrated circuit systems often include one or more processors, memory devices, and input / output devices that communicate with each other through a bus system. Each device includes an integrated circuit made up of an arrangement of logic gates, and each gate implements a logic function. The gates are interconnected and communicate with each other by changing state in unison at regular, timed intervals according to an internal clock signal. Information input to the integrated circuit, in the form of signals, is acted upon by the logic gates which produce new information as output signals. [0003] Digital integrated circuits are typically timed by a clock generator that functions through a phase-locked loop. The phase-locked loop locks an internal clock signal in phase and frequency to an external input clock. The phase-...

AI Technical Summary

Benefits of technology

The patent describes a way to receive two different clock signals and use them to create a single-ended output clock signal. This is done using a differential amplifier. The technical effect of this invention is to improve the accuracy and reliability of clock signals in electronic devices.

Problems solved by technology

However, the phase-locked loop has a lock time requirement that delays a start-up of an integrated circuit from an idle / power-down state, and is a sophisticated analog circuit that does not scale easily with process changes.

In generating such high frequencies the phase-locked loop can contribute to jitter in the internal clock signal, and also suffers from problems of instability and noise.

Images