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Nonvolatile memory and erasing method

a nonvolatile memory and information technology, applied in nanoinformatics, instruments, transistors, etc., can solve the problems of obstructing the realization of semiconductor memories with higher storage capacity, reducing control, and already up against difficulties in realizing finer storage elements

Inactive Publication Date: 2005-05-05
NAT UNIV CORP OSAKA KYOIKU UNIV THE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a way to quickly and selectively erase information written in a nonvolatile memory that uses bistable molecules for storage. The invention involves irradiating the bistable molecular layer of a memory cell with erase light while applying an electric field to only a portion of the layer that stores information to be erased. This method allows for efficient and selective erasure of information without affecting other information stored in the memory."

Problems solved by technology

On the other hand, realization of finer storage elements has been already up against a difficulty.
This obstructs realization of semiconductor memories with higher storage capacity.
Since the mechanical control considerably lowers an erasing speed, it is practically not possible to selectively erase a part of the information written in this nonvolatile memory.

Method used

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Embodiment Construction

[0017] An embodiment of the present invention will now be described with reference to the accompanying drawings. Incidentally, the constituent elements performing the same or similar functions are denoted by the same reference symbols in the respective drawings so as to avoid the overlapping description.

[0018]FIG. 1 is a cross-sectional view schematically showing a nonvolatile memory according an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a nonvolatile memory according to an embodiment of the present invention.

[0019] The nonvolatile memory 1 includes a semiconductor substrate 2. On the semiconductor substrate 2, formed are word lines WL, bit lines BL intersecting the word liens WL, transfer elements TR arranged in the vicinity of each intersection of the word line WL and the bit line BL, and first electrodes 3 connected to the bit lines BL via the transfer elements TR, respectively, and arranged in the column and row directions on one main surf...

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Abstract

There is provided a nonvolatile memory including memory cells each of which includes a storage element including a bistable molecular layer, wherein the bistable molecular layer contains a bistable molecule which brings about isomerization from a first isomer into a second isomer by injecting a hole and an electron into the bistable molecular layer, and brings about isomerization from the second isomer into the first isomer by irradiating the bistable molecular layer with erase light, and the memory is configured to irradiate the bistable molecular layers of all the memory cells with the erase light while applying an electric field to the bistable molecular layer of only a part of the memory cells that stores information to be held when erasing information stored in the rest of the memory cells.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2003-372662, filed Oct. 31, 2003, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a nonvolatile memory and an erasing method of erasing information written in the nonvolatile memory. [0004] 2. Description of the Related Art [0005] Each memory cell in semiconductor memories such as a DRAM (Dynamic Random Access Memory) or an EEPROM (Electrically Erasable Programmable Read-Only Memory) is usually composed of a transfer element such as a transistor and a storage element such as capacitor or a transistor with a floating gate. Semiconductor memories with high storage capacity have been conventionally realized by an advance of a fine processing technique, and it is expected that finer transfer elements would be realiz...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C16/02G11C13/02G11C13/04H01L27/28H01L51/05H10B69/00
CPCB82Y10/00G11C13/0014G11C13/041G11C13/04G11C13/02
Inventor TSUJIOKA, TSUYOSHI
Owner NAT UNIV CORP OSAKA KYOIKU UNIV THE