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Fast switching power insulated gate semiconductor device

Inactive Publication Date: 2006-06-08
NORTH WEST UNIV (ZA)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0005] Accordingly, it is an object of the present invention to provide an insulated gate device and method and circuit of driving such a device with which the applicant believes the aforementioned disadvantages may at least be alleviated.

Problems solved by technology

Capacitance inherent in the gate structures of insulated gate devices limits the switching speeds of these devices.
It has been found that such a ratio impairs the switching speed of these devices.
These times are too long for some applications.

Method used

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  • Fast switching power insulated gate semiconductor device
  • Fast switching power insulated gate semiconductor device
  • Fast switching power insulated gate semiconductor device

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Experimental program
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Embodiment Construction

[0039] A known insulated gate device in the form of a known power metal oxide silicon field effect transistor (MOSFET) is generally designated by the reference numeral 10 in FIG. 1.

[0040] The MOSFET 10 comprises a gate 12, a drain 14 and a source 16. The device 10 has a gate capacitance CG between the gate and the source.

[0041] It is well known that when a voltage VGS is applied to the gate as shown at 80 in FIG. 8(a), charge is deposited on the gate causing the device to switch on and a voltage VDS to switch from a maximum value shown at 82 to a minimum value shown at 84. Similarly, when the charge is removed from the gate, the device is switched off and the voltage VDS switches to the maximum value.

[0042] The total switching time Ts (illustrated in FIG. 8(a)) is constituted by the sum of a turn-on delay time Tdon and a rise time Tr. The turn-on delay time is defined to be the time between % rise of the gate-to-source voltage VGS above 10% of its maximum value and the onset of d...

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Abstract

An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (Cfiss) when the device is on and the input capacitance Ciiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer 32 at the gate having an effective thickness dins larger than a minimum thickness.

Description

TECHNICAL FIELD [0001] THIS invention relates to insulated gate semiconductor devices such as metal oxide silicon field effect transistors (MOSFET's), more particularly to such devices for use in power switching applications and to a method of driving such devices. BACKGROUND ART [0002] In known MOSFET structures, it is presently preferred to minimize the gate voltage VGS required for switching of the device and which then implies a relatively large input gate capacitance. [0003] Capacitance inherent in the gate structures of insulated gate devices limits the switching speeds of these devices. It is also well known that the Miller effect has an influence on the input capacitance at the gate of devices of the aforementioned kind in that the input capacitance of a typical commercially available MOSFET varies during switching of the device. The input capacitance has a first value Ciiss when the device is off and a second value Cfiss when the device is on. The ratio of the second and fi...

Claims

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Application Information

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IPC IPC(8): H01L27/148H01L25/07H01L29/423H01L29/78H03K17/0412
CPCH01L25/07H01L29/42364H01L29/7802H03K17/04123H01L2924/0002H01L2924/00
Inventor VISSER, BARENDDE JAGER, OCKER
Owner NORTH WEST UNIV (ZA)