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Processing a memory link with a set of at least two laser pulses

a memory link and laser pulse technology, applied in semiconductor lasers, semiconductor/solid-state device details, instruments, etc., can solve the problems of incomplete link severing, increased laser pulse energy, and deterioration of the quality of the device that includes the severed link, so as to improve the quality of laser processing of ic links.

Inactive Publication Date: 2006-06-29
SUN YUNLONG +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances the quality and precision of link severing, reduces the risk of substrate damage, and enables closer link placement, increasing circuit density while maintaining high processing speed.

Problems solved by technology

Such a conventional link processing laser pulse creates a large heat affected zone (HAZ) that could deteriorate the quality of the device that includes the severed link.
Increased laser pulse energy increases the damage risk to the IC chip.
However, using a laser pulse energy within the risk-free range on thick links often results in incomplete link severing.

Method used

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  • Processing a memory link with a set of at least two laser pulses
  • Processing a memory link with a set of at least two laser pulses
  • Processing a memory link with a set of at least two laser pulses

Examples

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Embodiment Construction

[0039]FIGS. 3-5, 9, 10B, 12, 14D, and 16C show power versus time graphs of exemplary sets 50a, 50b, 50c,50d, 50e, 50f, and 50g (generically sets 50) of laser pulses 52a, 52b1-52b8, 52c1-52c5, 52d1-52d3, 52e1-52e4, 52f1-52f2, and 52g1-52g2 (generically laser pulses 52) employed to sever links 22 in accordance with the present invention. Preferably, each set 50 severs a single link 22. Preferred sets 50 include 2 to 50 pulses 52. The duration of each set 50 is preferably shorter than about 1000 ns, more preferably shorter than 500 ns, and most preferably in the range of about 5 ns to 300 ns. Sets 50 are time-displaced by a programmable delay interval that is typically shorter than 0.1 millisecond and may be a function of the speed of the positioning system 62 and the distance between the links 22 to be processed. The pulse width of each laser pulse 52 within set 50 is in the range of about 100 fs to about 30 ns.

[0040] During a set 50 of laser pulses 52, each laser pulse 52 has insuff...

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Abstract

A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.1 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly link removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each link (22). Conventional IR wavelengths or their harmonics can be employed.

Description

RELATED APPLICATIONS [0001] This patent application is a continuation of U.S. patent application Ser. No. 10 / 322,347, filed Dec. 17, 2002, which claims priority from U.S. Provisional Application No. 60 / 341,744, filed Dec. 17, 2001, and is a continuation-in-part of U.S. patent application Ser. No. 09 / 757,418, filed Jan. 9, 2001, now U.S. Pat. No. 6,574,250, which claims priority from both U.S. Provisional Application No. 60 / 223,533, filed Aug. 4, 2000, and U.S. Provisional Application No. 60 / 175,337, filed Jan. 10, 2000.TECHNICAL FIELD [0002] The present invention relates to laser processing of memory or other IC links and, in particular, to a laser system and method employing a set of at least two laser pulses to sever an IC link on-the-fly. BACKGROUND OF THE INVENTION [0003] Yields in IC device fabrication processes often incur defects resulting from alignment variations of subsurface layers or patterns or particulate contaminants. FIGS. 1, 2A, and 2B show repetitive electronic cir...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/82B23K26/04B23K26/06B23K26/067H01L21/768H01L23/525H01S3/00
CPCB23K26/04B23K26/0604B23K26/0613B23K26/063B23K26/0635B23K26/067B23K26/365G03F7/70041G03F7/70725H01L21/76894H01L23/5258H01S3/005H01S3/0057H01S3/0085H01S3/0092H01S3/1118H01S3/2383H01S5/4012B23K26/0622B23K26/0624B23K26/361H01L2924/0002Y10S438/94H01L2924/00B23K26/362
Inventor SUN, YUNLONGSWENSON, EDWARD J.HARRIS, RICHARD S.
Owner SUN YUNLONG
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