Charge-trapping memory device

Abstract

An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source / drain junctions of transistors of the addressing circuitry.

Description

TECHNICAL FIELD [0001] This invention concerns memory devices comprising arrays of charge-trapping memory cells. BACKGROUND [0002] Nonvolatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon (U.S. Pat. Nos. 5,768,192, and 6,011,725, which are incorporated herein by reference). [0003] Charge carriers are accelerated from source to drain through the channel region and...

AI Technical Summary

Benefits of technology

"The present invention provides a charge-trapping memory device with improved retention after cycling values, especially an NROM cell comprising an oxide-nitride-oxide memory layer sequence. The invention also removes the difficulties deriving from the application of a nitride liner. An oxidized region underneath the nitride liner and especially the formation of lateral oxidized regions between the memory layer sequence and the nitride liner can prevent the loss of charge carriers from the memory layer into the liner nitride. The process option of radical-based oxidation can oxidize besides the bulk semiconductor material, preferably silicon, also the nitride of an oxide-nitride-oxide memory layer sequence and thus enable a spatial separation of the memory layer from the nitride liner. The invention thus provides a more robust and reliable memory device."

Problems solved by technology

However, a nitride liner, which is applied all over the surface of the device and thus covers also the area of the memory cell array, shows negative effects on the performance of the memory cell transistors.

This is supposed to cause poor values of retention after cycling (RAC), which is one of the key parameters to be optimized in a charge-trapping memory device.

Insufficient RAC values are probably related to a high trapping density of charge carriers in the nitride liner and / or to high mechanical stress caused by the nitride liner being deposited directly on the memory layer sequence so that a formation of leakage paths in the memory layer sequence may result.

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