Apparatus and method to trace high performance multi-issue processors

a processor and multi-issue technology, applied in the field of on-chip debugging, can solve problems such as difficulty in tracing sequential execution of programs, and achieve the effect of facilitating tracing

Inactive Publication Date: 2007-04-19
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006] One benefit of the present invention is that it facilitates tracing a complex multi-issue microprocessor having one or more features that may disrupt sequential execution of instructions, such as deep pipelines, multi-latency pipelines, multiple outstanding load misses, out-of-order (OOO) instructions, or superscalarity.

Problems solved by technology

However, high performance processors may include features that make it difficult to trace sequential execution of a program.

Method used

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  • Apparatus and method to trace high performance multi-issue processors
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  • Apparatus and method to trace high performance multi-issue processors

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Embodiment Construction

[0020] Embodiments of the invention are discussed in detail below. While specific implementations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the invention.

[0021]FIG. 1 illustrates a tracing system 100 that includes on-chip components identified as microprocessor core 110, trace generation logic (TGL) 120, trace control block (TCB) 130, and test access port (TAP) controller 140. TGL 120 can be embodied as part of microprocessor core 110. TGL 120 is generally operative to generate program counter (PC) and data trace information based on the execution of program code in one or more pipelines within microprocessor core 110. In some embodiments, microprocessor core 10 is a high performance multi-issue microprocessor having one or more features that may disrupt sequential execution of instruct...

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Abstract

A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Description

FIELD OF THE INVENTION [0001] The present invention relates generally to on-chip debugging, and more specifically to program counter (PC) and data tracing in embedded processor systems. BACKGROUND OF THE INVENTION [0002] Computer systems process information according to a program that includes a sequence of instructions defined by an application program or an operating system. Typically, a program counter provides a series of memory addresses that are used by the processor for fetching instructions stored in the associated memory. In this process, the processor conveys the memory address to the memory over an address bus, and the memory responds over an instruction / data bus with the instruction stored in the addressed memory location. The instructions stored in the memory constitute the program to be executed. [0003] Program development relies heavily on the verification of the instructions stored in memory as well as their corresponding execution. Typically, these debug efforts are...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/44
CPCG06F9/3836G06F11/3636G06F9/3855G06F9/3857G06F9/3856G06F9/3858
Inventor THEKKATH, RADHIKATREUE, FRANZKRAGH, SORENRAJAGOPALAN, VIDYA
Owner MIPS TECH INC
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