Modulation of stress in stress film through ion implantation and its application in stress memorization technique

Abstract

Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains / memorizes thereby increasing device performance.

Description

BACKGROUND OF INVENTION [0001] 1) Field of the Invention [0002] This invention relates generally to fabrication of semiconductor devices and more particularly to a method to change the stress in a stress layer over a FET device. [0003] 2) Description of the Prior Art [0004] Performance and economic factors of integrated circuit design and manufacture have caused the scale of elements (e.g. transistors, capacitors and the like) of integrated circuits to be drastically reduced in size and increased in proximity on a chip. That is, increased integration density and proximity of elements reduces the signal propagation path length and reduces signal propagation time and susceptibility to noise and increase of possible clock rates while the reduction in element size necessary for increased integration density increases to ratio of functionality which can be provided on a chip to the costs of production (e.g. wafer / chip area and process materials) per chip and, potentially, the cost of dev...

AI Technical Summary

Benefits of technology

[0013] Some of the example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over the NMOS transistor. A ion implant is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains / memorizes.

[0019] performing an anneal of the substrate and stress layer whereby the implant and anneal increase the stress on the channel region of the MOS transistor.

Problems solved by technology

That is, increased integration density and proximity of elements reduces the signal propagation path length and reduces signal propagation time and susceptibility to noise and increase of possible clock rates while the reduction in element size necessary for increased integration density increases to ratio of functionality which can be provided on a chip to the costs of production (e.g. wafer / chip area and process materials) per chip and, potentially, the cost of devices containing the chips by reducing the number of inter-chip and inter-board connections required.

This phenomenon is well-recognized and theories concerning the physical effects by which it occurs are, in any event, unimportant to its exploitation.

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