Interconnect structure having a silicide/germanide cap layer

Abstract

An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide / germanide.

Description

[0001]This application claims the benefit of U.S. Provisional Application No. 60 / 789,028, filed on Apr. 4, 2006, entitled “Interconnect Structure Having a Silicide / Germanide Cap Layer,” which application is hereby incorporated herein by reference.TECHNICAL FIELD[0002]This invention is related generally to integrated circuits, and more particularly to the structure and methods of interconnect structures in integrated circuits.BACKGROUND[0003]A conventional integrated circuit contains a plurality of patterns of metal lines separated by inter-wiring spacings and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type, according to current technology, may comprise eight or more l...

AI Technical Summary

Benefits of technology

[0015]With the silicide / germanide layers formed on top of the copper lines, the overall resistance and reliability of the interconnect structure are improved.

Problems solved by technology

However, copper still suffers from electro migration (EM) and stress migration (SM) reliability issues as geometries continue to shrink and current densities increase.

However, the introduction of cap layer 16 generates another problem.

A more severe problem is that the probability of via failure increases.

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