Method for manufacturing recess gate in a semiconductor device

Abstract

A method for manufacturing a recess gate in a semiconductor device includes forming a device isolation structure on a substrate to define an active region, forming a hard mask pattern over the substrate to selectively expose at least a portion of the active region, forming a recess pattern in the active region through an etching process using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulating layer over the substrate, and forming a gate electrode over the gate insulating layer to cover at least the recess pattern.

Description

RELATED APPLICATION[0001]CD This application claims the benefit of priority to Korean patent application number 10-2006-0096334, filed on Sep. 29, 2006, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Technical Field[0003]The present invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a recess gate in a semiconductor device.[0004]2. Description of the Related Art[0005]As semiconductor devices become highly integrated, transistor channel lengths are correspondingly shortened. Due to the shortening of the channel length, a short channel effect abruptly lowers threshold voltages more seriously in a conventional planar transistor.[0006]In addition, an electric field of a substrate becomes very high due to the excessive ion implantation as memory devices such as a dynamic random access memory (DRAM) become increasingly integrated. In particular, a junction leakage current incre...

AI Technical Summary

Benefits of technology

The present invention provides methods for manufacturing a recess gate in a semiconductor device that can prevent damage to a field oxide layer and physical damage to an active region where a storage node is formed, even if there is a partial overlay misalignment between the active region and a recess pattern. The methods involve forming a device isolation structure, a hard mask pattern, a recess pattern, a sacrificial sidewall, a bulb pattern, a gate insulating layer, and a gate electrode. The technical effects of the invention include preventing damage to the field oxide layer and physical damage to the active region, improving the reliability and performance of the semiconductor device.

Problems solved by technology

In addition, an electric field of a substrate becomes very high due to the excessive ion implantation as memory devices such as a dynamic random access memory (DRAM) become increasingly integrated.

In particular, a junction leakage current increases at a junction of a storage node contact SNC, which leads to a limitation of reduction of data retention time.

As the field oxide layer, over which passing gate P passes, is damaged, i.e., the recessed portion of field oxide layer 13 is deepened, and the device characteristic is deteriorated.

When a misalignment occurs while recessing the bulb-shaped recess gate, an active region around a field oxide layer, i.e., a region where the storage node will be formed, is eventually damaged.

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