Direct Radio Frequency (RF) Sampling With Recursive Filtering Method

Abstract

A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).

Description

[0001]This application is a divisional of prior U.S. application Ser. No. 10 / 190,867, filed Jul. 8, 2002, which claims priority to provisional application Ser. No. 60 / 312,602, filed Aug. 5, 2001, and Ser. No. 60 / 313,772, filed Aug. 20, 2001 and Ser. No. 60 / 348,902, filed Oct. 26, 2001. Each of these provisional applications is assigned to the assignee of this application and is also incorporated herein by reference as if each of the applications was reproduced in its entirety herein.FIELD OF THE INVENTION[0002]This invention relates generally to wireless communications systems, and particularly to direct sampling of radio frequency signals and filtering of same.BACKGROUND OF THE INVENTION[0003]Discrete-time radio frequency (RF) is a newly emerging field in wireless digital communications wherein analog RF signals that are transmitted over-the-air are directly sampled into a discrete-time sample stream suitable for digital signal processing. A typical wireless digital communications ...

AI Technical Summary

Benefits of technology

[0020]The present invention provides a number of advantages. For example, use of a preferred embodiment of the present invention allows the use of a single clock signal generated by one local oscillator in the generation of multiple clock signals, each with a different phase angle, rather than using different clock signals generated by the local oscillator in conjunction with separate clock generating hardware for each different lower frequency clock signal with a different phase angle. This results in a significant reduction in the amount of clock generating hardware, leading to a reduction in the overall size of the integrated wireless transceiver.

[0027]Also, use of a preferred embodiment of the present invention can reduce the effect of the overall noise in the system by stopping the sampling of the input signal. By stopping the sampling of the input signal, noise generated by a digital circuit is not combined with the input signal into a discrete-time sample stream. Due to the use of sampling capacitors that retains their accumulated charge for an extended period of time, the samples that occur during the period of digital noise may be replaced with samples of the input signal already sampled by the sampling capacitors, which are free of the digital noise.

Problems solved by technology

Unfortunately, analog circuit components, especially components such as capacitors, inductors, resistors, etc. necessary for the analog filters are difficult to integrate into an integrated circuit.

A reason for resetting the charge on the sampling capacitor is to prevent the excessive accumulation of charge during the sampling phase to saturate (or deplete) the charge storage capacity of the sampling capacitor, thus resulting in loss of information.

Once the sampling capacitor becomes saturated or depleted, information is lost.

A disadvantage of this technique is the amount of power consumed in bringing the sampling capacitor up to the bias voltage value.

Each time that the sampling capacitor is brought from zero volts to the bias voltage value, a significant amount of current is consumed.

This leads to the consumption of a considerable amount of power.

Therefore, the mixers can be quite complex, with four separate signal paths.

A significant disadvantage of having four separate signal paths in the mixer stems from the fact that each signal path requires a different clock.

However, the use of a different LO for each signal path can result in synchronization problems due to frequency differences in the signals generated by the different LOs, resulting in a degraded downconverted signal.

A major disadvantage in having separate clock generating hardware for each signal path is power consumption.

As expected, the clock generating hardware must also be clocked at high frequencies and hardware clocked at high frequencies consumes more power than hardware clocked at low frequencies.

Also for more complex clocking schemes, a large amount of hardware is required for the clock generating hardware.

The clocking at high operating frequencies and the redundancy of the generating hardware results in a significant amount of power consumption.

An additional disadvantage is that the redundant clock generating hardware also requires a lot of real estate when it comes time to integrate the mixer hardware into an integrated circuit.

The increased real estate results in a larger, more expensive device.

The processing of the discrete-time sample stream, once it is converted into a digital bit stream, by processing elements and digital signal processors, etc., can inject a significant amount of noise into the current-mode mixer.

If unattended to, the noise can have serious effects on the overall performance of the current-mode mixer and the entire device.

Although the bursts of digital activity may be only several nano-seconds in duration, the digital noise that is created by the bursts of activity may be periodic in nature and be of significant magnitude.

It is the periodic nature of the noise along with its impulse-like response that can degrade the overall performance of both the mixer and the digital device through the injection of a significant amount of noise into the discrete-time sample stream.

Unfortunately, the rings and wells cannot prevent noise that is carried on signal lines and power planes.

Additionally, the use of rings and wells may increase the overall cost of the integrated circuit, due to the requirement for additional steps in the fabrication process and increased complexity in the design of the integrated circuit itself.

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