Design method estimating signal delay time with netlist in light of terminal line in macro, and program

Abstract

A design method according to an aspect of the present invention includes laying out a plurality of functional blocks of a design circuit based on a first netlist, creating a second netlist by adding a first path information to the first netlist, the first path information corresponding to an inter-block line connecting between the functional blocks, creating a third netlist by adding a second path information to the second netlist, the second path information corresponding to an intra-block line connected to a terminal of each functional block from inside of each functional block, creating a fourth netlist that models a line resistance and a line capacitance of an inter-instance line which combines the first path information and the second path information included in the third netlist, and estimating a delay time from information based on the fourth netlist.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The present invention relates to a design method that estimates signal delay time by using a netlist which is created in light of terminal lines in a macro and a program. Particularly, the present invention relates to a design method that estimates signal delay time by using a netlist which is created in light of the capacitance and resistance of terminal lines in a macro and a program.[0003]2. Description of Related Art[0004]With the recent increase in scale of semiconductor integrated circuits (LSI: large scale integration), the function of the macro incorporated into the LSI to implement prescribed functions becomes complex. Further, with the recent miniaturization of the structure of the integrated circuit, the width of the internal lines narrows accordingly. Further, along with the increase of the scale and size of the macro itself, the line length from the first stage and the last stage in the macro to the external terminal of the...

AI Technical Summary

Benefits of technology

[0018]According to the present invention, the third netlist is created by adding the information of the line connected to the terminal of the functional block from inside of the functional block to the line resistance and the line capacitance between the functional blocks of the design circuit. Then, the fourth netlist in which the line resistance and the line capacitance are modeled is created based on the line information of the third netlist. By performing the modeling of the line based on the fourth netlist thus created, the line between the functional blocks and the line in the functional block can be integrally modeled. This increases the estimation accuracy of sig

Problems solved by technology

With the recent increase in scale of semiconductor integrated circuits (LSI: large scale integration), the function of the macro incorporated into the LSI to implement prescribed functions becomes complex.

Consequently, the capacitance and the resistance of the internal line affect signal delay more largely.

If the result of the delay simulation shows that delay is within the range of specification, the method ends the design.

However, it has now been discovered that since the related design method of Japanese Unexamined Patent Application Publication No. 11-259555 considers only the input terminal capacitance as the line delay component inside the macro, there is a large difference between the delay time of an actual LSI and the calculated value of the delay simulation and thereby the actual LSI does not operate in some cases.

It is necessary to perform the circuit design again in such a case, which increases a design period.

In order to prevent this error, it is necessary to place constraints to minimize the line length from the input terminal and output termina

Images