Flexible instruction processor systems and methods

Abstract

A design system for generating configuration information and associated executable code based on a customisation specification, which includes application information including application source code and customisation information including design constraints, for implementing an instruction processor using re-programmable hardware, the system comprises a template generator for generating a template for each processor style identified as a candidate for implementation; an analyser for analysing instruction information for each template and determining instruction optimisations; a compiler for compiling the application source code to include the instruction optimisations and generate executable code; an instantiator for analysing architecture information for each template, determining architecture optimisations and generating configuration information including the architecture optimisations; and a builder for generating device-specific configuration information from the configuration information including the architecture optimisations. In another aspect, a management system for managing run-time re-configuration of an instruction processor implemented using re-programmable hardware, comprises a configuration library containing configuration information for a plurality of instruction processor implementations; a code library for containing associated executable code for the implementations; a loader for loading application data and, as required, configuration information and associated executable code into re-programmable hardware for implementation and execution of an instruction processor; a loader controller for signalling the loader to load application data and, as required, configuration information and associated executable code, and execute the executable code; a run-time monitor for obtaining run-time statistics relating to operation of the instruction processor; an optimisation determiner configured to receive the run-time statistics, and being operable to instruct the loader to load new configuration information and associated executable code for a new implementation into the re-programmable hardware; and an optimisation instructor for invoking the optimisation determiner.

Description

RELATED APPLICATION DATA[0001]This application is a continuation of U.S. patent application Ser. No. 10 / 416,977, filed Oct. 30, 2003, which is a national phase of International Patent Application No. PCT / GB01 / 05080 filed Nov. 19, 2001, which U.S. patent application issued on Jun. 2, 2009 as U.S. Pat. No. 7,543,283, all of which are hereby incorporated by reference in their entireties.FIELD OF THE INVENTION[0002]The present invention relates to the design-time and run-time environments of re-programmable instruction processors, such instruction processors being referred in the specification as flexible instruction processors (FIPs).[0003]In one aspect the present invention relates to a FIP design system for generating FIP configuration information and associated executable FIP code for FIP implementations based on user-specified customisation specifications, and a related method of generating FIP configuration information and associated executable FIP code for FIP implementations bas...

AI Technical Summary

Benefits of technology

[0013]It is an aim of the present invention to provide design-time and run-time environments for flexible instruction processors (FIPs) which provide for user customisation and design-time optimisation, in order to exploit the re-programmability of current and future generations of re-programmable hardware.

Problems solved by technology

However, such processors have fixed architectures, and tend to lose performance when dealing with non-standard operations and non-standard data which are not supported by the instruction set formats [1].

However, the design and fabrication of such integrated circuits is still expensive, and, once designed, its customised function is fixed and cannot be altered.

This approach does not, however, encompass customising the overall architecture of the defined execution unit and programmable execution units, or the set of tools supporting such customisation.

This approach does not, however, encompass methods and tools for the automatic generation of processors customisable both at design and run time.

Automatic methods for producing compile-time and run-time customisable datapaths have also been developed [16], but the instruction set architectures (ISAs) in these designs are fixed, as implemented on a commercial microprocessor, for example, and the architecture is not customisable.

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