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Operating voltage tuning method for static random access memory

a random access memory and operating voltage technology, applied in static storage, information storage, digital storage, etc., can solve the problems of not providing enough information to shmoo test, designer's difficulty in adjusting corresponding process parameters, and shmoo test also cannot provide information regarding whether, so as to achieve the effect of lowering the operating voltage of the sram

Active Publication Date: 2010-06-03
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides an operating voltage tuning method for a static random access memory (SRAM) to lower the operating voltage. The method involves performing a shmoo test on the SRAM to obtain a shmoo test plot and a minimum operating voltage. The minimum operating voltage is then compared with a preset specification, and the process parameters of the SRAM are adjusted accordingly to achieve the minimum operating voltage. The method can effectively differentiate the factors that contribute to the minimum operating voltage of the SRAM, and can also be used to adjust the process parameters of the SRAM to optimize its performance.

Problems solved by technology

As a result, when the SRAM needs to operate on a lower operating voltage, a designer has difficulty adjusting corresponding process parameters.
Therefore, the shmoo test can not provide the designer enough information to properly adjust the process parameters of the SRAM corresponding to the SNM or the WNM and to further adjust the minimal operating voltage.
Meanwhile, the shmoo test also can not provide information regarding whether there are early fail bits inherent therein.

Method used

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  • Operating voltage tuning method for static random access memory
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  • Operating voltage tuning method for static random access memory

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Embodiment Construction

[0032]An illustration on the operating voltage tuning method for an SRAM according to the present invention is provided below along with several embodiments accompanied with diagrams for the better comprehension and implementation by those of ordinary skill in the art.

[0033]Referring simultaneously to FIG. 1 and FIG. 3A, FIG. 3A is a flow chart illustrating the operating voltage tuning method for an SRAM according to a first embodiment of the present invention. Although an SRAM 100 is considered as a circuit under test throughout the specification, those of ordinary skill in the art should realize that the SRAM 100 merely represents an SRAM having millions of bits or more. The actual circuit under test may be a combination of SRAM having an arbitrary number of bits.

[0034]In the first embodiment, steps of tuning an operating voltage of the SRAM 100 include the following. First, perform a shmoo test (step S320) on the plurality of the SRAM 100 to be tested, wherein the shmoo test perf...

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Abstract

An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a tuning method of process parameters of a memory and more particularly, to a tuning method of minimizing operating voltage for a static random access memory.[0003]2. Description of Related Art[0004]The Static Random Access Memory (SRAM) is a common random access memory. A feature of the SRAM lies in that as long as power is supplied to the SRAM, data stored in the SRAM will not be lost. This is different from a dynamic random access memory (DRAM) which has to periodically re-flash data lines. As a result, the SRAM still plays an irreplaceable role in today's electronic products.[0005]The common SRAM has a so-called 6T structure comprising six transistors. Referring to FIG. 1, FIG. 1 shows a circuit diagram of a conventional 6 T SRAM. FIG. 1 illustrates an SRAM 100 of size 1 bit. The SRAM 100 mainly comprises 4 transistors PL1, PD1, PL2, and PD2 which form a latched circuit to store data...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C29/00G11C5/14
CPCG11C11/413G11C29/02G11C2029/5604G11C29/028G11C29/56008G11C29/021
Inventor KUO, CHIEN-LILIU, FU-CHAOHOU, CHUN-LIANGHSIEH, MIN-CHIN
Owner UNITED MICROELECTRONICS CORP
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