Method and apparatus for reducing radiation and cross-talk induced data errors

Abstract

The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

Description

BACKGROUND INFORMATION[0001]This invention was made with Government support under NR0000-06-C-0248 awarded by the United States National Reconnaissance Office. The Government has certain rights in this invention.[0002]1. Field[0003]The present disclosure relates generally to the data processing field, and more particularly to a method and apparatus for reducing data errors caused by radiation particle strikes in integrated circuits.[0004]2. Background[0005]Spacecraft, such as satellites, space stations, space shuttles, rockets, and the like may have various operational systems. These operational systems may include systems for navigation and communication, and other environmental systems used for operating and protecting a spacecraft in space. Each of these operational systems may include computers, processors, controllers, and other electronic equipment that comprise integrated circuits.[0006]Radiation particles such as cosmic rays, protons trapped in the Van Allen belts, and parti...

AI Technical Summary

Benefits of technology

[0008]Thus, one or more of the different advantageous embodiments may provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

[0009]The different advantageous embodiments may further provide an integrated circuit comprising a number of dual interlocked storage cell flip-flops and a number of temporal filters. Each of the number of dual interlocked storage cell flip-flops has two inputs and four storage nodes. The four storage nodes include a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. A first two of the four storage nodes comprise a master dual interlocked storage cell latch and a second two of the four storage nodes comprise a slave dual interlocked storage cell latch. The number of temporal filters has two outputs. Each of the two outputs is connected to two inputs of a dual interlocked storage cell flip-flop in the number of dual interlocked storage cell flip-flops. Each input of the two inputs is connected to a corresponding storage node in the first two storage nodes of the master dual interlocked storage cell latch of the dual interlocked storage cell flip-flop. The number of temporal filters is physically located between a pair of circuit nodes in the number of pairs of circuit nodes forming the number of upsettable circuit node pairs within the dual interlocked storage cell flip-flop to increase critical node spacing.

[0010]The different advantageous embodiments may further provide a method for reducing data errors. A data signal is received. A first portion of the data signal is sent onto a first input path in a filter. The first input path comprises a first input of a first C-gate and a first input of a second C-gate. A second portion of the data signal is sent onto a second input path in the filter. The second input path comprises a number of delay elements in series with the first C-gate and the second C-gate. The second portion of the signal travels through the number of delay elements into a second input of the first C-gate and a second input of the second C-gate.

Problems solved by technology

Radiation particles such as cosmic rays, protons trapped in the Van Allen belts, and particles from solar particle events can cause errors in integrated circuits.

Radiation particle strikes can cause single event effects that upset storage circuits, register bits, and latches.

Radiation particle strikes in logic gates can create voltage transients, known as single event transients (SETs), that may be latched by storage circuits and cause a single event upset.

Single event upsets can cause incorrect output or incorrect operation of an integrated circuit.

This incorrect output or incorrect operation of an integrated circuit can lead to inconsistencies or incorrect behavior in the operation systems of a spacecraft, for example, such as loss of communication capability, corruption of transmitted or received data, or misguided navigation into an undesired orbit.

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