FPGA Co-Processor For Accelerated Computation

Abstract

A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA. A mechanical and electrical interface is for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard. After completion of a start-up cycle, the FPGA is configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.

Description

FIELDOne or more embodiments generally relate to accelerators and, more particularly, to a co-processor module including a Field Programmable Gate Array (“FPGA”).BACKGROUNDCo-processors have often been used to accelerate computational performance. For example, early microprocessors were unable to include floating-point computation circuitry due to chip area limitations. Doing floating-point computations in software is extremely slow so this circuitry was often placed in a second chip which was activated whenever a floating-point computation was required. As chip technology improved, the microprocessor chip and the floating-point co-processor chip were combined together.A similar situation occurs today with specialized computational algorithms. Standard microprocessors do not include circuitry for performing these algorithms because they are often specific to only a few users. By using an FPGA (field programmable gate-array) as a co-processor, an algorithm can be designed and program...

AI Technical Summary

Benefits of technology

One or more embodiments generally relate to accelerators and, more particularly, to a co-processor module including a Field Programmable Gate Array (“FPGA”).

A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a

Problems solved by technology

For example, early microprocessors were unable to include floating-point computation circuitry due to chip area limitations.

Doing floating-point computations in software is extremely slow so this circuitry was often placed in a second chip which was activated whenever a floating-point computation was required.

Standard microprocessors do not include circuitry for performing these algorithms because they are often specific to only a few users.

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