Substrate edge treatment for coater/developer

a substrate edge and coater technology, applied in photomechanical treatment, instruments, electrical equipment, etc., can solve the problems of inability to achieve resist pattern accuracy, inability to remove metal at wafer end, and inability to solve protection film at substrate edg

Inactive Publication Date: 2012-03-29
TAKEISHI TOMOYUKI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This method effectively removes residues and organic films from the substrate edge, reducing particle contamination and improving semiconductor device yield by ensuring complete development and cleaning of the edge area, thereby enhancing the accuracy of resist patterns and reducing device contamination.

Problems solved by technology

Further, removal of a metal at a wafer end has been also a problem in a liquid immersion exposure tool that has recently come into practical use.
On the other hand, in liquid immersion exposure, an accuracy of a resist pattern cannot be possibly obtained because of, e.g., elution of a photosensitive agent or the like contained in a resist film into water, or penetration of water into the resist film.
In particular, in case of using the developer soluble type protection film, when a developer is supplied to an upper side of a water-repellent protection film in a developing treatment after liquid immersion exposure, since the developer is repelled on a surface of the protection film from a substrate edge, the protection film cannot be sufficiently solved at the substrate edge and it may possibly remains as a residue even after end of the developing treatment.
These protrusions become particles to disadvantageously contaminate a carriage portion and others in an etching device.
Further, when an etching step or the like is carried out in this state, the organic film remaining at the substrate edge become particles to disadvantageously contaminate a carriage portion or the like in an etching device.

Method used

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  • Substrate edge treatment for coater/developer
  • Substrate edge treatment for coater/developer
  • Substrate edge treatment for coater/developer

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0037]As shown in a process flowchart of FIG. 1, an anti-reflection film coating material (e.g., ARC29A manufactured by NISSAN CHEMICAL INDUSTRIES, LTD.) is dropped and rotated to spread on a semiconductor substrate, and then a heat treatment is carried out to form an anti-reflection film having a film thickness of 80 nm (ST101). An ArF chemically amplified resist film containing an acid producing agent is formed with a film thickness of 170 nm on the anti-reflection film (ST102). Further, a developer soluble type protection film (e.g., TILC019 manufactured by TOKYO OHKA KOGYO CO., LTD.) is formed with a film thickness of 140 nm on the ArF chemically amplified resist film (ST103).

[0038]In more detail, the anti-reflection film, the chemically amplified resist, and the developer soluble type protection film are formed in accordance with a procedure of spreading each material on a treatment target substrate by a spin coat method and effecting a heat treatment to remove a solvent contai...

second embodiment

[0053]A second embodiment uses the cleaning treatment system and the cleaning treatment described in conjunction with the first embodiment to remove a resist film that has entered a space between protrusions formed at a substrate edge by a reactive ion etching (RIE) device at the time of resist coating.

[0054]For example, when forming a trench capacitor, a silicon nitride film and a silicon oxide film are sequentially formed on a silicon substrate surface by a hot wall type CVD device or the like. Then, coating / exposure / development of a resist film is performed on the silicon oxide film to form a resist pattern. However, the resist film may remain at a position where the resist film does not essentially remain at a substrate edge in some cases. In this state, the resist pattern is used as a mask to sequentially etch the silicon oxide film, the silicon nitride film, and the silicon substrate, thereby forming a trench serving as a capacitor. At this time, the resist film remaining at t...

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Abstract

A method of substrate edge treatment includes forming a processing target film on a treatment target substrate, applying an energy line to a predetermined position on the processing target film to form a latent image on the processing target film, heating the treatment target substrate in which the latent image is formed on the processing target film, developing the processing target film after the heating, inspecting whether a residue is present at an edge of the treatment target substrate after the developing, and cleaning an end of the treatment target substrate to remove the residue at the edge of the treatment target substrate determined to be defective in the inspecting.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-039361, filed Feb. 16, 2006, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a substrate edge treatment, and more particularly to a substrate edge treatment having a step of removing surface roughness of a substrate or a film that has adhered to the substrate.[0004]2. Description of the Related Art[0005]In a manufacturing process of a semiconductor device, an unnecessary part of a metal thin film formed at an end of a semiconductor wafer may be removed by etching in some cases. Various proposals have been conventionally made to suppress unintentional etching at the center of a wafer surface involved by scattering of an etchant in this process (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2001-118824 or Jpn. P...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G03F7/38H01L21/02
CPCG03F7/2028H01L21/6715H01L21/67051G03F7/3021
InventorTAKEISHI, TOMOYUKIKOBAYASHI, YURI
OwnerTAKEISHI TOMOYUKI