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Single event upset hardened static random access memory cell

a memory cell and single event technology, applied in static storage, information storage, digital storage, etc., can solve the problems of ineffective damping of seu, srams are more susceptible to single event upsets (seus) or soft errors, and conventional six-transistor memory cells employing cross-coupled resistor based isolation

Active Publication Date: 2012-05-17
BAE SYST INFORMATION & ELECTRONICS SYST INTERGRATION INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is about a type of memory cell that is designed to prevent errors caused by single events. The cell includes two inverters that are connected in a way that reduces the impact of errors. The cell also includes resistors and a capacitor to help reduce errors. Overall, this design improves the reliability and accuracy of the memory cell.

Problems solved by technology

In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, SRAMs are more susceptible to single event upsets (SEUs) or soft errors.
Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset.
In addition, as the channel widths of transistors scale below 250 nm range, conventional six-transistor memory cells employing cross-coupled resistor based isolation do not effectively dampened SEU anymore.

Method used

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  • Single event upset hardened static random access memory cell
  • Single event upset hardened static random access memory cell
  • Single event upset hardened static random access memory cell

Examples

Experimental program
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second embodiment

[0021]Referring now to FIG. 2b, there is illustrated a circuit diagram of an SEU- hardened SRAM cell, in accordance with the present invention. As shown, an SRAM cell 20′ is similar to SRAM cell 20 from FIG. 2a. The difference between SRAM cell 20′ and SRAM cell 20 is that SRAM cell 20′ includes a capacitor Cm connected between node n1 and node n2.

[0022]Capacitor Cm is preferably made of metal-insulator-metal (MIM) because it occupies less physical area. However, capacitor Cm may be constructed with materials other than aluminum and a dielectric insulator. Other structures that may be used for capacitor Cm include poly-poly capacitors, trench capacitors, etc. In addition, capacitor Cm can be physically placed, for example, above transistors 21-24 in a vertical dimension in order to share the same silicon footprint with transistors 21-24.

[0023]MIM capacitor Cm provides positive feedback during an SEU event on a positively biased drain of one of transistors 22 or 24 storing a “1” in S...

third embodiment

[0024]With reference now to FIG. 2c, there is illustrated a circuit diagram of an SEU-hardened SRAM cell, in accordance with the present invention. As shown, an SRAM cell 20″ is similar to SRAM cell 20′ from FIG. 2b. The difference between SRAM cell 20″ and SRAM cell 20′ is that SRAM cell 20″ includes two additional capacitors C1 and C2. Preferably, capacitor C1 is connected to node n1, and capacitor C2 is connected to node n2.

[0025]As has been described, the present invention provides a SEU-hardened memory cell to be utilized in SRAMs. The present invention may be implemented in a variety of apparatuses having an SRAM. For example, referring now to FIG. 3, there is depicted a block diagram of an apparatus in which an SRAM may be incorporated. As shown, the apparatus includes an electronic system 70 coupled to a memory device 60. Electronic system 70 may be, for example, a processor, a memory controller, a chip set or any system that stores data in a memory device such as memory dev...

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Abstract

A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of a the second transistor. The second resistor is also connected between a gate of a the first transistor and the drain of the fourth transistor.

Description

PRIORITY CLAIM[0001]The present application claims priority under 35 U.S.C. §119(e)(1) to provisional application No. 60 / 891,246 filed on Feb. 23, 2007, the contents of which are incorporated herein by reference.STATEMENT OF GOVERNMENT INTEREST[0002]The present invention was made with United States Government support under contract number DTRA01.03.D.0007.0001 awarded by the Defense Threat Reduction Agency. The United States Government has certain rights in the present invention.BACKGROUND OF THE INVENTION[0003]1. Technical Field[0004]The present invention relates to memory circuits in general, and in particular to static random access memory circuits. Still more particularly, the present invention relates to single event upset hardened static random access memory cells.[0005]2. Description of Related Art[0006]Static random access memories (SRAMs) that employ conventional six- transistor memory cells are commonly utilized in electronic devices for storing information. In certain env...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C5/06G11C11/00G11C11/40
CPCG11C11/4125
Inventor LAWSON, DAVID C.ROSS, JASON F.
Owner BAE SYST INFORMATION & ELECTRONICS SYST INTERGRATION INC