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Semiconductor device and method for manufacturing semiconductor device

a semiconductor and semiconductor technology, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of incompatible attempts with the advanced cmos process of the 90 nm generation or later, and the need for high temperature annealing

Inactive Publication Date: 2012-08-16
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to diffuse the dopant for a long distance, annealing is required to be performed at a high temperature for a long time.
However, such attempts are incompatible with an advanced CMOS process of the 90 nm generation or later.

Method used

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  • Semiconductor device and method for manufacturing semiconductor device
  • Semiconductor device and method for manufacturing semiconductor device
  • Semiconductor device and method for manufacturing semiconductor device

Examples

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first embodiment

[0035]FIGS. 1A to 1F are cross-sectional views of a semiconductor substrate and illustrate main processes of a method for manufacturing a semiconductor device according to a

[0036]With reference to FIG. 1A, a silicon substrate 1 is etched to form an isolation trench. Then, the isolation trench is filled with an oxide film or the like to form an isolated region STI by shallow trench isolation, thereby defining active regions. Various transistors are formed on a plurality of the active regions. A process for manufacturing an n-channel high breakdown-voltage transistor will be mainly described hereinafter. A p-type dopant, for example B, is ion-implanted into the active region for a high breakdown-voltage transistor with acceleration energy in the range from 100 keV to 200 keV in a dose amount in the range from 2×1013 (hereinafter described in a manner such as 2E13) to 5E13 (cm−2), thereby forming a p-type well PW. In the case of production of a discrete device, this process may be omit...

third embodiment

[0053]In a portable wireless device, various MOS transistors are required to be integrated on a single silicon chip. For example, a middle breakdown-voltage transistor used for input and output (I / O) of a voltage of about 3.5 V is integrated with a low breakdown-voltage transistor used for a logic circuit as well as a high breakdown-voltage transistor used for a power amplifier. FIGS. 4A to 4I are perspective views illustrating main processes of a method for manufacturing a semiconductor device according to a

[0054]With reference to FIG. 4A, the isolated region STI is formed on the substrate 1 by the shallow trench isolation, thereby defining active regions. The active region in a left side is a core transistor region, and the middle active region is an I / O transistor region, and the active region in a right side is a high breakdown-voltage transistor region. In this case, an example of formation of an n-channel transistor will be described. The p-type dopant, for example B, is ion-i...

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PUM

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Abstract

A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional of application Ser. No. 12 / 882,038, filed Sep. 14, 2010, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-213189 filed on Sep. 15, 2009, the entire contents of which are incorporated herein by reference.FIELD[0002]The present invention relates to a semiconductor device and to a method for manufacturing the semiconductor device.BACKGROUND[0003]In a semiconductor integrated circuit, a MOS transistor that is driven with a higher voltage is often required as well as a MOS transistor that is driven with a low voltage. In cases where an input and output voltage of an external circuit is approximately 3.5 V, a middle breakdown-voltage MOS transistor that is driven with a voltage of approximately 3.5 V is required. Thus, a MOS transistor that is driven with a voltage higher than such a voltage may be required.[0004]In a power amplifier transistor that is mo...

Claims

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Application Information

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IPC IPC(8): H01L21/336
CPCH01L21/26586H01L21/823412H01L21/823418H01L21/823807H01L21/823814H01L27/0922H01L29/66477H01L29/456H01L29/4933H01L29/665H01L29/66659H01L29/7835H01L29/66492H01L29/1045
Inventor SHIMA, MASASHI
Owner FUJITSU SEMICON LTD