Test structure and methodology for three-dimensional semiconductor structures

Abstract

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 935,724, filed Nov. 6, 2007 the entire content and disclosure of which is incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention generally relates to structures and methodology for testing three-dimensional semiconductor structures having multiple functional layers.BACKGROUND OF THE INVENTION[0003]Test structures are typically allocated little space in a single layer semiconductor design, physical space being at a premium. Consequently, incorporation of a large test structure or a test structure integrally formed with and located near a functional semiconductor circuit into the single layer semiconductor design are economically prohibitive.[0004]Three dimensional semiconductor structures address such needs by providing an integrally formed test structures located in a peripheral testing layer that is formed above or below a functional layer ...

AI Technical Summary

Benefits of technology

This design simplifies the testing process, reduces manufacturing complexity, and enhances yield by eliminating the need for repeated carrier attachments and detachments, while providing adequate mechanical support for the semiconductor structure.

Problems solved by technology

Consequently, incorporation of a large test structure or a test structure integrally formed with and located near a functional semiconductor circuit into the single layer semiconductor design are economically prohibitive.

Scanning of the test patterns across the semiconductor circuit typically requires at least as many clock cycles as the number of gates per scan chain, and takes a significant amount of test time.

Each of the bonding steps and separation steps involve processing steps that consumes processing time as well as introducing factors that degrade yield of the exemplary prior art semiconductor structure.

Further, in the case of the repeated boding and separation of the C4 carrier substrates, the same C4 balls 30′ are employed in each round of the bonding and separation, which tends to degrade yield of the later bonding processes.

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