Field-effect transistor and manufacturing method thereof

a field-effect transistor and manufacturing method technology, applied in the field of transistors, can solve the problems of reducing productivity, increasing the unit cost of a manufacturing process, and the inability to apply different thicknesses of insulating films below field electrodes, so as to improve the breakdown voltage characteristic of an element, improve productivity, and improve the effect of power

Inactive Publication Date: 2014-02-06
ELECTRONICS & TELECOMM RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Enables adjustable insulating film thicknesses under field electrodes, improving breakdown voltage characteristics and enabling high-performance transistors with increased productivity and uniformity.

Problems solved by technology

Accordingly, in a case of a conventional manufacturing method of a field-effect transistor including a field electrode, it is impossible to apply different thicknesses of an insulating film below field electrodes, to the same element.
This causes a problem such as an increase in a unit cost of a manufacturing process and a reduction of productivity.

Method used

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  • Field-effect transistor and manufacturing method thereof
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  • Field-effect transistor and manufacturing method thereof

Examples

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Embodiment Construction

[0025]Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The configuration and operation effects of the present invention will be clearly understood through the detailed description as below.

[0026]FIGS. 2A to 2I are views illustrating a method for manufacturing a field-effect transistor according to one embodiment of the present invention.

[0027]As shown in FIG. 2A, on a semiconductor substrate 20, an active layer 21 and a cap layer 22 are sequentially formed. As shown in FIG. 2B, a region where a source•drain ohmic metal layer 23 is to be formed is defined as a source•drain pattern, which is deposited with an ohmic metal, and then is formed with the source•drain ohmic metal layer 23 through rapid thermal annealing (RTA), etc. Herein, in a manufacturing process of a high electron mobility transistor (HEMI) element using a gallium nitride (GaN)-based compound semiconductor, as an ohmic metal, a metal layer forme...

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Abstract

Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based on and claims priority from Korean Patent Application No. 10-2010-0130291, filed on Dec. 17, 2010, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a transistor, and more particularly to a field-effect transistor and a manufacturing method thereof, in which a separate lithography process and its corresponding additional process are not required, and insulating films below field electrodes have different thicknesses.[0004]2. Description of the Prior Art[0005]FIGS. 1A to 1H are views illustrating a method for manufacturing a field-effect transistor, according to a prior art.[0006]As shown in FIG. 1A, on a semiconductor substrate 10 including gallium nitride (GaN), silicon (Si), silicon carbide (SiC), semi-insulating gallium arsenide (GaAs), etc., a...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L29/78
CPCH01L29/7831H01L29/2003H01L29/404H01L29/42316H01L29/66462H01L29/66863H01L29/7787H01L29/812H01L29/7783
InventorAHN, HOKYUNLIM, JONG-WONYOON, HYUNG SUPMIN, BYOUNG-GUELEE, SANG-HEUNGKIM, HAE CHEONNAM, EUN SOO
OwnerELECTRONICS & TELECOMM RES INST