Package carrier and manufacturing method thereof

Abstract

A manufacturing method of a package carrier is provided. An insulation substrate having an upper surface, a lower surface, plural cavities located at the lower surface and plural through holes passing through the insulation substrate and respectively communicating with the cavities is provided. Plural vias is defined by the cavities and the through holes. A conductive material filling up the vias is formed to define plural conductive posts. An insulation layer having a top surface and plural blind vias extending from the top surface to the conductive posts is formed on the upper surface. A patterned circuit layer filling up the blind vias, being connected to the conductive posts and exposing a portion of the top surface is formed on the top surface. A solder mask layer is formed on the patterned circuit layer and has plural openings exposing a portion of the patterned circuit layer to define plural pads.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwan application serial no. 101128619, filed on Aug. 8, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND

[0002] 1. Field of the Invention

[0003] The invention relates to a package structure and a manufacturing method thereof, and more particularly, to a package carrier and a manufacturing method thereof.

[0004] 2. Description of Related Art

[0005] The purpose of chip package is to protect exposed chips, to reduce contact density in a chip, and to provide good thermal dissipation for chips. A leadframe serving as a carrier of a chip is usually employed in a conventional wire bonding technique. As contact density in a chip gradually increases, the leadframe which is unable to satisfy current demands on the high contact density is replaced by a package carrier which can achieve favorable contact den...

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