Soft pin insertion during physical design

Abstract

A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input net, and another is inserted at a fixed location proximate the output net and is interconnected with the output net. Cell placement is then optimized while maintaining the virtual pins at their fixed locations. More than two virtual pins may be inserted to bound a cluster of logic. The virtual pins may lie along the input / output nets. Pseudo-net weights are assigned to pseudo-nets formed between a cell and the virtual pins, and the pseudo-net weight can be increased for each placement iteration.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to a method of placing components of an integrated circuit design in a layout.[0003]2. Description of the Related Art[0004]Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cel...

AI Technical Summary

Benefits of technology

This invention is about a way to make sure that logic in an integrated circuit design is placed stable. It works by adding virtual pins to the circuit description, which are connected to the input and output of the logic. These virtual pins are then used to optimize the placement of cells in the circuit while keeping the virtual pins in their fixed locations. More than two virtual pins can be added to bound a cluster of logic. If the optimization is done to minimize wirelength, a weight is assigned to each connection between a cell and a virtual pin. This weight is increased for each placement iteration. This invention can make it easier to design and test new logic paths in integrated circuits.

Problems solved by technology

An IC may include a very large number of cells and require complicated connections between the cells.

Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers.

However, physical synthesis can take days to complete, and the computational requirements are increasing as designs are ever larger and more gates need to be placed.

There are also more chances for bad placements due to limited area resources.

Balancing the slack leads to a better placement of logic clusters timing-wise but it may break critical logic paths, sometimes referred to architectural logic paths.

Images