Transistor, resistance variable memory device including the same, and manufacturing method thereof

Abstract

A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C, 119(a) to Korean application number 10-2013-0021164, filed on Feb. 27, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Technical Field[0003]Exemplary embodiments of the present invention relate to a semiconductor integrated circuit device, and more particularly, to a transistor, and a resistance variable memory device including the same, and a manufacturing method thereof.[0004]2. Related Art[0005]With the rapid development of mobile and digital information communication and consumer-electronic industry, studies on existing electronic charge controlled-devices are expected to encounter the limitation. Thus, new functional memory devices of new concept other than the existing electronic charge devices need to be developed. In particular, next-generation memory devices with large capacity, ultra-high speed, ...

AI Technical Summary

Benefits of technology

[0013]According to still another aspect of an exemplary embodiment of the present invention, a method of manufacturing a resistance variable semiconductor device may include forming a source region in a semiconductor substrate, forming a semiconductor layer on the source region, patterning the semiconductor layer to form an active pillar, forming a first gate electrode to surround the active pillar, surrounding an upper region of the first gate electrode with an insulating layer while exposing a lower region of the first gate electrode, and forming a second gate electrode by increasing a work function of the exposed first gate electrode.

Problems solved by technology

With the rapid development of mobile and digital information communication and consumer-electronic industry, studies on existing electronic charge controlled-devices are expected to encounter the limitation.

However, even in the 3D vertical transistors, thin gate insulating layers may be required.

Thus, when a high voltage is supplied to a gate, a high electric field is applied to a lightly doped drain (LDD) region and gate induced drain leakage (GIRL) may be caused.

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