Method of fabricating integrated circuit

Abstract

A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates generally to a method of fabricating an integrated circuit, and more specifically to a method of fabricating an integrated circuit relating to the alignment of photoresist patterns.[0003]2. Description of the Prior Art[0004]In the fabrication of semiconductor integrated circuits (ICs), semiconductor devices are connected by several metallic interconnecting layers commonly referred to as multi-level interconnects. A damascene process is a convenient and predominant method for forming the multi-level interconnects. The damascene process includes etching a dielectric material layer to form trench and / or via patterns, filling the patterns with conductive materials such as copper, and performing a planarization process. Thus a metal interconnect is obtained.[0005]Photolithography is an essential process in the fabrication of semiconductor ICs. Principally, photolithography forms designed pattern...

AI Technical Summary

Benefits of technology

The present invention provides a method of fabricating an integrated circuit that makes use of double patterning processes and a third reticle to form a pattern that overlaps both the first and second patterns. By aligning the third reticle to both the first and second alignment marks, a compromising correction value can be obtained. This compromising correction value is then used to form the third pattern by aligning the third reticle with the resolution of the first and second patterns. This method allows for more precise patterning in the fabrication of integrated circuits.

Problems solved by technology

Subsequently, by performing semiconductor processes such as ion implantation, etching processes, or deposition, the complicated and sophisticated IC structure is obtained.

With the miniaturization of semiconductor devices and corresponding progress in fabrication methods, conventional lithography processes have met a bottleneck due to printability and manufacturability.

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