Manufacturing method of wafer level package structure

Abstract

A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 105104081, filed on Feb. 5, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION[0002]Field of the Invention[0003]The invention relates to a manufacturing method of a package structure, and particularly relates to a manufacturing method of a wafer level package structure.[0004]Description of Related Art[0005]In a manufacturing process of a wafer level package (e.g., fan out wafer level package (FO-WLP)), in order to support the wafer after thinning, the wafer is usually placed on a wafer support system (WSS). In this way, the wafer is able to withstand various transport in the manufacturing process and avoid wafer warpage which may cause fragmentation.[0006]FIG. 1A to FIG. 1G are schematic diagrams of a manufacturing process of a conventional wafer...

AI Technical Summary

Benefits of technology

The invention provides a method for making a wafer level package structure that is cheaper and easier to manufacture. The method uses a supporting board made of dummy silicon and a resin called a DAF to hold and protect the chip. This supporting board is used to make a flat platform for the chip, which prevents thickness variations and ensures the pads on the chip are exposed. This allows for a more efficient molding process and eliminates the need for additional conductive pillars or grinding after molding. The method is simpler, cheaper, and more clean compared to previous methods.

Problems solved by technology

However, if the flatness of the wafer support system 11 is worse, the required height of the conductive pillars 24 or the RDL 40 is higher, thereby increasing the package cost.

Thus, the process of removing the wafer support system 11 also requires a certain cost.

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