Integrated circuit having improved electromigration performance and method of forming same

a technology of integrated circuits and electromigration, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of reducing the durability and reliability of interconnects, forming voids within the entire interconnect structure, and accelerating grain growth

Inactive Publication Date: 2017-08-17
ALSEPHINA INNOVATIONS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional annealing at temperatures higher than about 100° C. results in faster grain growth and, consequently, larger grains but leads to forming voids within the entire interconnect structure.
However, any metal void formed within the interconnect structure drastically degrades durability and reliability of interconnects.
As metal atoms spread to the exterior of the metal due to electromigration, the resulting tensile stresses in the metal cause voids to be created within the metal, resulting in interconnect and / or chip failures.

Method used

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  • Integrated circuit having improved electromigration performance and method of forming same
  • Integrated circuit having improved electromigration performance and method of forming same
  • Integrated circuit having improved electromigration performance and method of forming same

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Embodiment Construction

[0014]The present disclosure relates to integrated circuits, and more particularly, to integrated circuits having a metal with a reduced grain size and a method of forming the same.

[0015]Aspects of the present disclosure provide an integrated circuit having a reduced electromigration effect. The electromigration phenomenon can be used to enhance microwave annealing of the conducting wires if the anneal is performed with an overburden intact, in which said overburden provides a source of metal atoms to replace voids and / or vacancies created by a microwave annealing current, and the combined thickness of the metal conductor and overburden is less than or comparable to the microwave skin depth of the conductor metal. Specifically, the present disclosure provides for a microwave treatment process as an alternative to and / or in addition to the conventional furnace anneal. The microwave annealing results in a reduction in the grain size of the metal within the interconnect which reduces t...

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Abstract

An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

Description

BACKGROUND[0001]Technical Field[0002]The present disclosure relates to integrated circuits, and more particularly, to integrated circuits having an improved electromigration performance and a metal with an increased grain size, and a method of forming the same.[0003]Related Art[0004]Integrated circuit interconnects, and particularly, high performance conductors are used for most types of advanced integrated circuits and are typically fabricated having thick metal wires such as copper (Cu) or aluminum (Al). Traditionally, the metal wires are formed using electrolytic plating processes in conjunction with photoresist masking and stripping, and removing a seed layer later on. In damascene processes, metal interconnect lines are delineated and isolated in dielectrics by means of chemical mechanical polishing (CMP). A dual damascene process is a similar process in which metal interconnect lines and vias (i.e., conductor-filled channels) are defined independently in photolithography and e...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/528H01L21/768H01L23/532
CPCH01L23/5283H01L23/53238H01L21/76877H01L21/76843H01L23/53252H01L21/2885H01L23/53209H01L21/76883
Inventor NAG, JOYEETARAY, SHISHIR K.SIMON, ANDREW H.GLUSCHENKOV, OLEGKRISHNAN, SIDDARTH A.CHUDZIK, MICHAEL P.
Owner ALSEPHINA INNOVATIONS INC
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