Semiconductor memory device and weak cell detection method thereof

Abstract

A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application No. 10-2016-0060016, filed on May 17, 2016, which is incorporated herein by reference in its entirety.BACKGROUND1. Field[0002]Exemplary embodiments of the present invention relate generally to a semiconductor designing technology, and more particularly, to a method for detecting a weak cell in a semiconductor memory device.2. Description of the Related Art[0003]Each memory cell of a semiconductor memory device, such as a dynamic random access memory (DRAM) device, generally includes a capacitor for storing data in the form of charges and a transistor functioning as a switch for controlling the flow of charges to and from the capacitor. Whether a data is in a ‘high logic’ level (i.e., logic ‘1’) or a ‘low logic’ level (i.e., logic ‘0’) is decided based on whether the capacitor stores the charges or not, in other words, whether the terminal voltage of the capacitor is high...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor memory device and method that can quickly detect weak cells during a test mode. The device includes memory blocks, shared bit-line sense amplifiers, and a word line driver for activating unshared word lines. The bit-line data is then compressed and detected by a weak cell detection circuit. The technical effect of the invention is to improve the efficiency and reliability of the memory device by identifying and eliminating weak cells during production.

Problems solved by technology

Hence, the data stored in the capacitor may be lost without supplementing the stored charges.

Meanwhile, when the individual data retention times of weak memory cells included in a memory device is less than the reference retention time of the device, data errors may occur in the weak cells of the memory device, and thus, the memory device including the weak memory cells should be detected and abandoned.

Without an accurate test for detecting the weak memory cells in a semiconductor memory device, the reliability of the semiconductor memory device is damaged.

Also, generally, reliability problems due to weak memory cells may worsen as memory cell density increases.

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