Method for operating low-current eeprom array

Abstract

A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.

Description

BACKGROUND OF THE INVENTIONField of the Invention[0001]The present invention relates to a memory array, particularly to a method for operating a low-current EEPROM (Electrically Erasable Programmable Read Only Memory) array.Description of the Related Art[0002]The CMOS (Complementary Metal Oxide Semiconductor) technology has been a normal process for fabricating ASIC (Application Specific Integrated Circuit). Flash memories and EEPROM (Electrically Erasable Programmable Memory) have been widely used in electronic products because their data will not volatilize but can be erased and programmed electrically.[0003]Non-volatile memories are programmable, storing charges to vary gate voltages of transistors, or not storing charges to preserve the original gate voltages of transistors. In erasing a non-volatile memory, the charges stored in the non-volatile memory are eliminated to resume the initial state of the memory. The flash memory architecture has advantages of small size and low co...

AI Technical Summary

Benefits of technology

The present invention provides a way to operate a low-current EEPROM array with low-current, low-voltage, and low-cost. A special bias is used to achieve the writing and erasing of bytes. This method allows for efficient and effective use of EEPROM arrays in various applications.

Problems solved by technology

However, the flash memory architecture does not allow erasing or programming a single one-bit memory cell but allows erasing or programming a block of the memory.

Therefore, the flash memory architecture is inconvenient in application.

Thus, the cost of using EEPROM is increased.

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