Liquid crystal display panel and manufacturing method thereof
a technology manufacturing method, which is applied in the field can solve the problems of unfavorable narrowing difficult to continue narrowing of panel frame, and narrow frame width of display panel, so as to achieve effective improvement of liquid crystal display panel product yield, reduce processing relating to gold ball, and effectively narrow external space of panel
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embodiment 1
[0032]Referring to FIG. 6 to FIG. 8, FIG. 6 is a schematic bonding diagram of a liquid crystal display panel according to an embodiment of the present disclosure. FIG. 7 is a schematic structural diagram of two conducted substrates in a liquid crystal display panel according embodiment 1 of the present disclosure. FIG. 8 is a schematic planar diagram of an external setting of the liquid crystal display panel in FIG. 7.
[0033]As shown in FIG. 6, the liquid crystal display panel comprises a first substrate 61, a second substrate 62, and a liquid crystal layer 63 disposed between the two substrates. The two substrates are paired to form a liquid crystal box. A closed ring pattern of a sealing bezel adhesive layer 64 is formed on surrounding (non-display area) of the liquid crystal display panel by a sealing material (sealant), and the liquid crystal layer 63 is sealed therein. A side bond pad 65 is disposed on one side surface of the liquid crystal display panel which is used to bond a ...
embodiment 2
[0039]Referring to FIG. 9 and FIG. 10, FIG. 9 is a schematic structural diagram of two conducted substrates in a liquid crystal display panel according embodiment 2 of the present disclosure. FIG. 10 is a schematic planar diagram of an external setting of the liquid crystal display panel in FIG. 9. The difference from the embodiment as shown in FIG. 7 is that, in the embodiment, the common voltage signal line on the COF is electrically connected to the CF substrate-side transparent conductive layer (CF-ITO), and meanwhile is connected to the TFT array substrate-side common voltage signal line, so that the driver IC can input common voltage signals into the plane through the CF-ITO and the TFT array substrate-side common voltage signal line at the same time.
[0040]Specifically, a CF substrate 91 includes a first base substrate 911 and a first transparent conductive layer (ITO) 912 disposed on the first base substrate 911. The first transparent conductive layer 912 includes a first com...
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Abstract
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