Semiconductor device and manufacturing method thereof
a technology of semiconductors and manufacturing methods, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve problems such as performance enhancement, and achieve the effect of enhancing performan
Active Publication Date: 2022-06-09
POWERCHIP SEMICON MFG CORP
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- Abstract
- Description
- Claims
- Application Information
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Benefits of technology
[0004]The disclosure provides semiconductor device and a manufacturing method thereof capable of providing enhanced performance.
[0025]To sum up, the embedded silicon germanium having the tip acts as the source / drain region in the disclosure. Further, the epitaxial layer is introduced between the upper surface of the substrate and the spacer wall, and through the introduction of the epitaxial layer, the overall height is increased when the source / drain region is manufactured. In such a design, the distance between the tip of the source / drain region and the channel region may be effectively decreased, stress application performed by the source / drain region may be improved, hole mobility may be increased, and performance of the semiconductor device may further be enhanced.
Problems solved by technology
Therefore, how to further improve the structure of the source region or the drain region (embedded silicon germanium) of a semiconductor device to achieve performance enhancement is an important issue.
Method used
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[0029]Directional terminology (e.g., top, down, right, left, front, rear, top, and bottom) is used with reference to the orientation of the figure(s) being described. As such, the directional terminology is used for purposes of illustration and is in no way limiting.
[0030]Unless otherwise clearly indicated, any method provided in this disclosure should not be construed as requiring steps therein to be performed in a particular order.
[0031]The disclosure is more comprehensively described with reference to the figures of the present embodiments. However, the disclosure can also be implemented in various different forms, and is not limited to the embodiments in the present specification. Thicknesses, dimensions, and sizes of layers or regions in the drawings are exaggerated for clarity. The same reference numbers are used in the drawings and the description to indicate the same or like parts, which are not repeated in the following embodiments.
[0032]FIG. 1A to FIG. 1H each is a partial...
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Abstract
A semiconductor device including a substrate, a gate structure, a source / drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source / drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source / drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source / drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.
Description
CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwanese application serial no. 109143094, filed on Dec. 7, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUNDTechnical Field[0002]The disclosure relates to a device and a manufacturing method thereof, and in particular, relates to a semiconductor device and a manufacturing method thereof.Description of Related Art[0003]At present, the embedded silicon germanium (embedded SiGe, eSiGe) process is deployed most of the time to form the source / drain region in a semiconductor device because in this way, compressive stress in the channel region may be raised, hole mobility may be increased, and the operating speed may be improved. Nevertheless, continuous technology advancement has led to increasing demand for enhanced performance of semiconductor devices. Therefore, how to further improve the str...
Claims
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IPC IPC(8): H01L29/78H01L29/08H01L29/165H01L29/66H01L21/02
CPCH01L29/7848H01L29/0847H01L21/02639H01L29/66636H01L21/02532H01L29/165H01L29/6656H01L29/6653H01L29/66628
Inventor LIANG, YI-CHUNG
Owner POWERCHIP SEMICON MFG CORP