Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation

Abstract

Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≦80PTs) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

Description

FIELD OF DISCLOSUREThe present disclosure of invention relates generally to monolithic integrated circuits, and more specifically to a repeated macrocell module design for use within Programmable Logic Devices (PLD's).The disclosure relates even more specifically to a macrocell module design as applied to a subclass of PLD's known as Complex Programmable Logic Devices (CPLD's) and High-Density Complex Programmable Logic Devices (HCPLD's).CROSS REFERENCE TO CO-OWNED APPLICATIONSThe following copending U.S. patent applications is owned by the owner of the present application, and its disclosure is incorporated herein by reference:(A) Ser. No. 09 / 927,793 filed Aug. 10, 2001 by Om P. Agrawal et al. and which was originally entitled, “Enhanced Macrocell Module Having Expandable Product Term Sharing Capability For Use in High Density CPLD Architectures”.CROSS REFERENCE TO PATENTSThe disclosures of the following U.S. patents are incorporated herein by reference:(A) U.S. Pat. No. 6,150,841 ...

AI Technical Summary

Benefits of technology

The present invention provides techniques for improving the design of CPLDs by allowing the use of fast paths, allowing for automatic re-routing of output signals, global distribution of output signals, two-stage steering, and unidirectional super-allocation. Additionally, the invention concentrates the development of complex function signals within singular logic blocks to avoid consuming inter-block interconnect resources. The CPLD configuring method involves identifying middle-complexity functions that can be implemented by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block, and configuring the CPLD accordingly. Overall, the invention enhances the performance and efficiency of CPLDs.

Problems solved by technology

In various instances, the CPLD configuring software may find that it cannot complete its mission successfully on a first try.

Moreover, if the CPLD does not have enough resources, the CPLD configuring software may find that it has exhausted CPLD resources (e.g., inter-block interconnect) without completing the to-be-implemented design.

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