Echo canceller and compression operators cascaded in time division multiplex voice communication path of integrated access device for decreasing latency and processor overhead

Abstract

A cascaded signal processing arrangement processes digitally encoded voice samples transported over a time division multiplex (TDM) communication path for application to a processor-controlled digital communication device, in particular an integrated access device. Processed voice samples are packetized in accordance with an encapsulating protocol and transmitted as a packetized voice output stream to a destination receiver device. The arrangement includes an echo canceller coupled to the TDM communication path and performing echo cancellation processing on the digitally encoded voice samples. The echo cancellation-processed voice sample signals are compressed by a data compression operator and applied to a packet encapsulating host processor via the TDM communication path. This obviates the necessity of the host processor having to use data bus cycles to download processed digitized voice samples.

Description

FIELD OF THE INVENTION[0001]The present invention relates in general to communication systems and subsystems therefor, and is particularly directed to a time division multiplexed (TDM) transport path-cascaded echo canceller and compression arrangement for use with an integrated access device (IAD), which operates directly on a TDM encoded voice stream to produce a processed digitized voice signal stream, so as to avoid burdening the host processor with having to use data bus cycles to extract the processed digitized voice samples.BACKGROUND OF THE INVENTION[0002]The ability to conduct high-speed data communications between relatively remote data processing systems and associated subsystems is currently a principal requirement of a variety of industries and applications, such as business, educational, medical, financial and personal computer users. Moreover, it can be expected that present and future applications of such communications will continue to engender more such systems and ...

AI Technical Summary

Benefits of technology

[0008]The respective gate arrays are interfaced with the TDM bus on their upstream and downstream ends by way of two full TDM ports, which may be configured as conventional serial-to-parallel and parallel-to-serial conversion and associated signal encoding format (e.g., mu-law) circuits. This allows each of the echo cancellation and compression operators to operate directly on the data transported by any channel of the TDM voice sample signal stream, and produces processed digitized voice signal data that is then placed back in the same channel of the TDM stream for transport directly to the host processor's communication co-processor. This avoids burdening the host processor with having to use data bus cycles to extract the data, as in the DSP array based architecture of FIG. 2.

Problems solved by technology

Now although these signal processing operators are available commercially as off-the-shelf components, they are usually based around a relatively costly digital signal processor (DSP) that occupies a substantial amount of circuit board real estate and consumes a large amount of power.

However, the most undesirable attribute of such DSP-based operators is the fact that the downstream host processor, to which the data produced by the echo cancellation and compression engines of the DSP array is to be delivered, is burdened with the responsibility for performing data bus cycles in order to read the data.

Because the host processor must execute data bus cycles to read the digitized voice sample data produced by the DSP array, it suffers a relatively large performance burden which increases the latency of the system.

Images