Pseudo SRAM

Abstract

A unit memory cell for use in a pseudo static random access memory (SRAM) includes a cell capacitor; a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor; and a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.

Description

FIELD OF INVENTION[0001]The present invention relates to a semiconductor memory device; and, more particularly, to a pseudo static random access memory.DESCRIPTION OF PRIOR ART[0002]A random access memory (RAM) is a semiconductor memory device for storing an input data in a memory cell array. Herein, each memory cell has an address to be selected.[0003]Generally, there are two different kinds of the RAM, i.e., one is a static random access memory (SRAM) and the other is a dynamic random access memory (DRAM). A memory cell of the SRAM has a static latching structure so that the data content of the memory cell can be maintained while a power is supplied to the SRAM. Herein, the memory cell of the SRAM includes four or six transistors (generally said to be a 4T or 6T structure).[0004]Meanwhile, a memory cell of the DRAM includes a single transistor and a single capacitor (generally said to be a 1T1C structure). Therefore, a conventional memory cell of the SRAM requires about 10 times l...

AI Technical Summary

Benefits of technology

[0027]It is, therefore, an object of the present invention to provide a pseudo SRAM for preventing an increase of an access time due to a refresh operation.

Problems solved by technology

Accordingly, an operating performance of the conventional SRAM is degraded due to the increase of the read / write cycle time.

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