Systems and methods for partial retention synthesis

Abstract

A retention synthesis application provides a means of analyzing a circuit design, functional test sequences, and the associated power specification to identify registers that do not need retention when a block is powered down. Reducing the number of retention registers reduces power consumption and chip area. The retention synthesis application is based, at least in part, upon symbolic simulation. In symbolic simulation, a symbol is used to represent a value that can be either 0 or 1 and the propagation of symbols is traced through the simulation.

Description

RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application Ser. No. 61 / 844,979, filed Jul. 11, 2013, entitled METHODS FOR AUTOMATICALLY SELECTING REGISTERS FOR PARTIAL STATE RETENTION, the entire disclosure of which is herein incorporated by reference. This application also claims the benefit of U.S. Provisional Application Ser. No. 61 / 908,233, filed Nov. 25, 2013, entitled METHODS FOR PARTIAL RETENTION SYNTHESIS, the entire disclosure of which is also herein incorporated by reference.FIELD OF THE INVENTION[0002]The present invention relates generally to integrated circuit design and, more particularly, to techniques for determining non-retention and retention registers.BACKGROUND OF THE INVENTION[0003]In integrated circuit design, it is desirable to minimize the power that is used by maximizing efficiency of a chip. One way to do this is to minimize the number of registers that are “retention” registers (meaning, they retain data when no power is ...

AI Technical Summary

Benefits of technology

The systems and methods in this patent analyze a circuit design, test sequences, and power specification to identify which registers in the circuit need to be retained and which ones can be eliminated. By doing so, the circuits can be produced more efficiently and cost-effectively.

Problems solved by technology

In the mobile electronics area where battery-driven devices are ubiquitous, power consumption has become one of the major concerns when designing circuits.

One major problem with this power-off approach is that information in power-down blocks will be completely lost.

When the block is needed again, it will be in a non-deterministic state, producing unpredictable circuit behavior.

However, this design implementation may not be optimal because some registers do not need retention if their values are updated before the registers are first read after power-up.

It is possible to manually inspect a design to select registers that do not need retention, however that is time-consuming and tremendously error-prone.

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