Multi-bank testing apparatus for a synchronous dram

Abstract

A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in accordance with an increased memory integration degree. The multi-bank testing apparatus includes a row address strobe generating unit for enabling a word line to transmit data from cells to bit line sense amplifiers in each bank of the synchronous DRAM, a column address strobe generating unit for generating a signal adapted to enable transistors respectively adapted to couple bit lines carrying data, amplified by the bit line sense amplifiers, to local data bus lines, input / output sense amplifiers for amplifying data on the local data bus lines, respectively, a transmission gate unit for controlling transmission of data from the input / output sense amplifiers to global read data bus lines, and an input / output comparing unit for compressing data from the input / output sense amplifiers prior to the transmission thereof to the global read data lines.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to an apparatus for testing a synchronous dynamic random access memory (DRAM) which is a semiconductor memory, and more particularly to a multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in accordance with an increased memory integration degree.[0003]2. Description of the Related Art[0004]Generally, a synchronous DRAM includes a plurality of row address strobe (RAS) generating circuits corresponding respectively to banks of the synchronous DRAM. Each of the RAS-generating circuits is enabled in response to a bank selection address signal adapted to select a bank associated with the RAS-generating circuit, thereby establishing row paths for the selected bank. Th...

AI Technical Summary

Benefits of technology

[0016]Therefore, the present invention has been made in view of the above-mentioned problems involved in conventional techniques, and an object of the invention is to provide a multi-bank testing apparatus for a synchronous DRAM which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in accordance with an increased memory integration degree.

Problems solved by technology

This results in a lengthened test time.

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