Phase locked loop circuit

Abstract

A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator, a first charge pump for increasing / decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing / decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter. In this PLL circuit, when the phase difference between the reproduced data pulse and the VCO clock is within the pull-in range of the phase comparator, the operation of the frequency comparator is restricted by the output of the phase comparator. Therefore, the PLL circuit can perform stable data reading even when the reproduced data pulse has a large amount of clock jitter.

Description

[0001]This is a reissue application of U.S. Pat. No. 6,489,851, issued Dec. 3, 2002, and a divisional application of U.S. Reissued Pat. No. RE39,807, issued Sep. 4, 2007. FIELD OF THE INVENTION[0002]The present invention relates to a phase locked loop circuit (hereinafter referred to as “PLL-circuit”) for generating an output signal having no lags in frequency and phase from those of an input signal, which is used in a magnetic disk unit such as an optic disk unit.BACKGROUND OF THE INVENTION[0003]A recent CD (Compact Disk) player is capable of normal-speed playback when reading audio data from a CD, and 32X-speed playback when reading computer data from a CD. In such a CD player capable of playing both of a CD containing audio data and a CD containing computer data, when playing the disk at 32X speed, the maximum frequency of the reproduced data pulse read from the disk of the reproduced data pulse read from the disk becomes 32 times as high as that at the normal-speed playback and,...

AI Technical Summary

Benefits of technology

The present invention provides a PLL circuit for a magnetic disk unit that can limit the operation of a frequency comparator when there is a difference in phases between the reproduced data pulse and the VCO clock, and lock the phases even when there is a lot of jitter in the data. This results in stable data reading. The PLL circuit includes a frequency comparator, a phase comparator, a selector, two charge pumps, a loop filter, and a voltage controlled oscillator. The frequency comparator detects phase sections of the clock corresponding to the leading edge and the trailing edge of the reproduced data pulse and outputs a frequency error level as a frequency comparison error signal. The selector thins the frequency comparison error signal when there is a change between specific phase sections of the clock. This prevents unnecessary frequency fluctuation and ensures stable data reproduction.

Problems solved by technology

In the aforementioned PLL circuit X, however, since the range of adaptable frequency bands is broad, fluctuations in the output from the first charge pump 4 for controlling the VCO 7 according to the output of the frequency comparator 1 are increased, whereby the range of fluctuations in the output from the loop filter 6 for smoothing the output of the first charge pump 4 becomes wide, resulting in an unstable PLL circuit.

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