3results about How to "Improve compilation speed" patented technology

The present application belongs to the technical field of knowledge compilation and network reliability analysis, and particularly relates to a network reliability intelligent computing method and system for a logical decision graph, comprising: modeling a network system as a triple data structure composed of a network topology graph, a terminal node set and an edge availability probability set; determining a topology order of network nodes and network edges based on the triple data structure; constructing a full binary tree vtree with leaf nodes corresponding to network edges one by one according to the topology order; and compiling the network topology graph into a zero-suppression statement logical decision graph using the vtree, wherein the zero-suppression statement logical decision graph is used to represent a set of valid subgraphs that satisfy terminal node connectivity; and recursively calculating a reliability value of the network system based on the zero-suppression statement logical decision graph.

The application provides a RT-THREAD resident system based on D1-H, which comprises a user module and a BIOS module, wherein the BIOS module comprises a hardware abstraction layer, an RTOS layer, and an API layer; the RTOS layer comprises an RT-Thread kernel, a thread management unit, a synchronization and communication unit, a clock management unit, and a memory management unit; the hardware abstraction layer comprises a driver construction, a software component, and a BootLoader; and the API layer comprises a driver component interface, a software component interface, and an RTOS service calling interface.The application has the advantages of reducing the programming threshold, improving the portability of application programs, and improving the compiling speed; the starting process after the RT-Thread is resident is analyzed, a resident test experiment is designed taking the synchronization and communication as an example, and the test result proves the feasibility of the RT-Thread resident.

A loop vectorization method and apparatus are disclosed. The loop vectorization method includes: in response to determining that the current loop can be rolled back, creating a first data structure corresponding to the current loop after the loop rollback; for the current loop and the first data structure, determining the maximum vectorization factor and candidate vectorization factors of the current loop that will not cause register overflow, respectively; determining the optimal vectorization factor from the candidate vectorization factors; in response that the optimal vectorization factor is a candidate vectorization factor determined for the first data structure, performing a loop rollback on the current loop to reduce the number of registers used in each iteration of the current loop after the loop rollback; selectively performing loop unrolling on the current loop after the loop rollback to obtain a first target loop; and performing a vectorization transformation on the first target loop based on the optimal vectorization factor.