Stable semiconductor storage device with pseudo storage unit

Abstract

The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to 'H' level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.

Description

technical field [0001] The present invention relates to a static semiconductor memory device, in particular, to a memory cell having a memory cell disposed at the intersection of a word line and a first and second bit line and a memory cell disposed at the intersection of the word line and the first and second dummy bit line A static semiconductor memory device of a dummy memory cell. Background technique [0002] Conventionally, in order to achieve high speed and low power consumption of a static random access memory (hereinafter referred to as SRAM), a method using a dummy memory cell has been proposed. For example, Japanese Patent Application Laid-Open No. 11-339476 discloses a method for setting dummy memory cells. When the word line corresponding to the address signal is at a selection level, the dummy memory cells and normal memory cells are simultaneously activated to output a prescribed readout signal. According to this method, when the word line is at the selection...

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Problems solved by technology

However, in this document, since the dummy memory cell is activated by the dummy word line, the dummy bit line is pulled down at a timing earlier than the activation timing of the normal memory cell.

Thus, for the offset, although the tolerance can be improved by equalizing the pull-down speed of a plurality of dummy memory cells, it is necessary to consider the difference in the rising timing of the dummy word line and the normal word line for design. When changing the configuration of the memory cell array, there are The timing problem had to be reworked

In order to correspond to various bit and word structures required by system LSI, etc., it is necessary to individually design the optimum timing, which prolongs the design and development cycle

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