Bus data transmission standard coordination method, central processing unit and bridging chips

Abstract

This invention provides a bus data transmission specification coordinate method and central process unit, bridge chip and a bus connected with above two using the method. The method comprises the following steps: first enter the computer into a system coordinate state; to make one from central process unit and bridge chip send signal to the other one with a data transmission specification storage unit; to let the storage unit send out responding second signal to the first signal; after deciding the bus data transmission specification, to jump the system coordinate system and transmit the data with the bus data transmission specification.

Description

technical field [0001] The invention relates to a bus data transmission specification coordination method and a central processing unit and a bridge chip applied thereto, especially a bus data transmission specification coordination method applied between the central processing unit and the bridge chip in a computer system. Background technique [0002] The mainboard of the general computer sold on the market now is basically composed of a central processing unit (Central Processing Unit, referred to as CPU), a chipset (chipset) and some peripheral circuits. The central processing unit is the entire computer. The core of the computer, the main job is to process and control the operation of each part of the entire computer, as well as to perform logical operations; while the chipset is responsible for connecting the operation between the central processing unit and other interface devices. There are also many different ways to combine chipsets. At present, chipsets composed o...

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Problems solved by technology

However, it can be seen from the above paragraph that if the two signals are transmitted with different front-end bus widths, the system composed of the two will not work properly.

That is, in FIG. 2( c), the data information of 64 bits transmitted by the north bridge chip 20 cannot allow the central processing unit 10 to transmit the data bus 222 with a width of 32 bits, and the address information in the central processing unit 10 is Transmission with the address bus 221 of 13-bit width, but at the north bridge chip 20 is transmitted with the address bus 221 of 32-bit width, so under the existing system design, the central processing unit 10 and the north bridge chip 20 They cannot work normally with each other. The similar situation is shown in Figure 2(d), and the same result is obtained

[0006] Due to the popularization of some personal peripheral mobile computing (mobile computing) accessories on the market, such as: PDA (Personal Digital Assistant) or notebook computers, etc., and in order to cater to the concept of thinner and lighter volume, smaller printed circuits are required Boards or chips with fewer pins are used to match, so that the central processing units designed by various manufacturers also tend to have fewer and fewer pins. For example, the design with 32 bits as the width of the front bus, as shown in the figure The block diagram in 2(b) can represent it; on the other hand, in order to achieve better performance, some desktop application systems may have to use chips with more pins, such as the width of the front bus is at least The 128-bit transmission mode is not 64-bit or 32-bit; but when transmitting with different front-end bus widths, the above-mentioned problems will occur, so it is easy to cause inconvenience to users, and it is also important for manufacturers of bridge chips. In other words, it is necessary to produce different types of bridge chips corresponding to different types of central processing units. In this way, different types of bridge chips cannot support different types of central processing units, making these unusable bridge chips a production problem. waste on

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